riscv: dts: starfive: Add crypto and DMA node for VisionFive 2

[platform/kernel/linux-starfive.git] / arch / riscv / boot / dts / starfive / jh7110.dtsi

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 1f9fd1e..cdf7fa9 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -632,6 +632,33 @@
                                 <&syscrg JH7110_SYSRST_WDT_CORE>;
                };
 
+               crypto: crypto@16000000 {
+                       compatible = "starfive,jh7110-crypto";
+                       reg = <0x0 0x16000000 0x0 0x4000>;
+                       clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
+                                <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
+                       clock-names = "hclk", "ahb";
+                       resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
+                       dmas = <&sdma 1 2>, <&sdma 0 2>;
+                       dma-names = "tx", "rx";
+               };
+
+               sdma: dma@16008000 {
+                       compatible = "arm,pl080", "arm,primecell";
+                       arm,primecell-periphid = <0x00041080>;
+                       reg = <0x0 0x16008000 0x0 0x4000>;
+                       interrupts = <29>;
+                       clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
+                                <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
+                       clock-names = "hclk", "apb_pclk";
+                       resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
+                       lli-bus-interface-ahb1;
+                       mem-bus-interface-ahb1;
+                       memcpy-burst-size = <256>;
+                       memcpy-bus-width = <32>;
+                       #dma-cells = <2>;
+               };
+
                rng: rng@1600c000 {
                        compatible = "starfive,jh7110-trng";
                        reg = <0x0 0x1600C000 0x0 0x4000>;