Merge branch 'CR_1176_CLOCK_TREE_PLL_Xingyu.Wu' into 'jh7110-5.15.y-devel'

[platform/kernel/linux-starfive.git] / arch / riscv / boot / dts / starfive / jh7110.dtsi

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index c02c4a1..847a92e 100755 (executable)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -290,6 +290,8 @@
                                "stg_apb", "clk_rtc",
                                "gmac0_rmii_refin", "gmac0_rgmii_rxin";
                        #clock-cells = <1>;
+                       starfive,sys-syscon = <&sys_syscon 0x18 0x1c
+                                       0x20 0x24 0x28 0x2c 0x30 0x34>;
                        status = "okay";
                };