"mipitx_dphy_rxesc",
"mipitx_dphy_txbytehs";
#clock-cells = <1>;
- status = "disabled";
+ status = "okay";
};
clkisp: clock-controller@19810000 {
reg = <0x0 0x19810000 0x0 0x10000>;
reg-names = "isp";
#clock-cells = <1>;
+ clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
+ <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
+ <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
+ clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
+ "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
+ "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi";
+ resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
+ <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
+ reset-names = "rst_isp_top_n", "rst_isp_top_axi";
status = "disabled";
};
status = "disabled";
};
+ sec_dma: sec_dma@16008000 {
+ /*compatible = "arm,pl080", "arm,primecell";*/
+ compatible = "starfive,pl080";
+ reg = <0x0 0x16008000 0x0 0x4000>;
+ reg-names = "sec_dma";
+ interrupt-parent = <&plic>;
+ interrupts = <29>;
+ clocks = <&oscclk>;
+ clock-names = "apb_pclk";
+ lli-bus-interface-ahb1;
+ /*lli-bus-interface-ahb2;*/
+ mem-bus-interface-ahb1;
+ /*mem-bus-interface-ahb2;*/
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ #dma-cells = <2>;
+ /*status = "disabled";*/
+ };
+
+ crypto: crypto@16000000 {
+ compatible = "starfive,jh7110-sec";
+ reg = <0x0 0x16000000 0x0 0x4000>,
+ <0x0 0x16008000 0x0 0x4000>;
+ reg-names = "secreg","secdma";
+ interrupts = <28>, <29>;
+ interrupt-names = "secirq",
+ "dmairq";
+ clocks = <&clkgen JH7110_SEC_HCLK>,
+ <&clkgen JH7110_SEC_MISCAHB_CLK>;
+ clock-names = "sec_hclk","sec_ahb";
+ resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
+ reset-names = "sec_hre";
+ status = "disabled";
+ };
+
i2c6: i2c@12060000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x12060000 0x0 0x10000>;
mailbox_contrl0: mailbox@0 {
compatible = "starfive,mail_box";
reg = <0x0 0x13060000 0x0 0x0001000>;
+ clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
+ clock-names = "clk_apb";
+ resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
+ reset-names = "mbx_rre";
interrupts = <26 27>;
#mbox-cells = <2>;
status = "disabled";
status = "disabled";
};
- encoder: display-encoder {
- compatible = "starfive,display-encoder";
+ dssctrl: dssctrl@295B0000 {
+ compatible = "verisilicon,dss-ctrl", "syscon";
+ reg = <0 0x295B0000 0 0x90>;
+ };
+
+ hdmi_output: hdmi-output {
+ compatible = "verisilicon,hdmi-encoder";
+ verisilicon,dss-syscon = <&dssctrl>;
+ verisilicon,mux-mask = <0x70 0x380>;
+ verisilicon,mux-val = <0x40 0x280>;
status = "disabled";
};
- dc8200@29400000 {
+ dc8200: dc8200@29400000 {
compatible = "verisilicon,dc8200";
- reg = <0x0 0x29400000 0x0 0x100>,<0x0 0x29400800 0x0 0x2000>;
+ reg = <0x0 0x29400000 0x0 0x100>,
+ <0x0 0x29400800 0x0 0x2000>,
+ <0x0 0x17030000 0x0 0x1000>;
interrupts = <95>;
+ status = "disabled";
+ clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
+ <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
+ <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
+ <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
+ <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
+ <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
+ <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
+ <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
+ <&clkgen JH7110_VOUT_SRC>,
+ <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
+ <&clkgen JH7110_AHB1>,
+ <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
+ <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
+ <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
+
+ <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
+ <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
+ <&clkvout JH7110_U0_DC8200_CLK_AXI>,
+ <&clkvout JH7110_U0_DC8200_CLK_CORE>,
+ <&clkvout JH7110_U0_DC8200_CLK_AHB>;
+ clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
+ "noc_disp","noc_isp","noc_stg","vout_src",
+ "top_vout_axi","ahb1","top_vout_ahb",
+ "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
+ "axi_clk","core_clk","vout_ahb";
+
+ resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
+ <&rstgen RSTN_U0_DC8200_AXI>,
+ <&rstgen RSTN_U0_DC8200_AHB>,
+ <&rstgen RSTN_U0_DC8200_CORE>,
+ <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
+ <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
+ <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
+ <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>,
+ <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>,
+ <&rstgen RSTN_U0_JTAG2APB_PRESETN>,
+ <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
+ <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>,
+ <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>,
+ <&rstgen RSTN_U0_NOC_BUS_DDRC_N>;
+ reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
+ "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
+ "rst_noc_gpu","rst_noc_vdec","rst_jtag2apb",
+ "rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc";
+
+
+ };
+
+ mipi_dphy: mipi-dphy@295e0000{
+ compatible = "starfive,jh7100-mipi-dphy-tx";
+ reg = <0x0 0x295e0000 0x0 0x10000>;
+ /*clocks = <&uartclk>, <&apb2clk>;*/
+ /*clock-names = "baudclk", "apb_pclk";*/
+ clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
+ clock-names = "dphy_txesc";
+ resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
+ <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
+ reset-names = "dphy_sys",
+ "dphy_txbytehs";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi_dsi: mipi@295d0000 {
+ compatible = "cdns,dsi";
+ reg = <0x0 0x295d0000 0x0 0x10000>;
+ reg-names = "dsi";
+ /*clocks = <&apb1clk>, <&apb2clk>;*/
+ /*clock-names = "dsi_p_clk", "dsi_sys_clk";*/
+ clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
+ <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
+ <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
+ <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
+ clock-names = "sys",
+ "apb",
+ "txesc",
+ "dpi";
+ resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
+ <&rstgen RSTN_U0_CDNS_DSITX_APB>,
+ <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
+ <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
+ <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
+ <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
+ reset-names = "dsi_dpi",
+ "dsi_apb",
+ "dsi_rxesc",
+ "dsi_sys",
+ "dsi_txbytehs",
+ "dsi_txesc";
+ phys = <&mipi_dphy>;
+ phy-names = "dphy";
+ status = "disabled";
port {
- #address-cells = <1>;
- #size-cells = <0>;
- dc_out_dpi0: endpoint@0 {
- /*reg = <0>;
- remote-endpoint = <&hdmi_input>;*/
- };
- dc_out_dpi1: endpoint@1 {
- /*reg = <1>;
- remote-endpoint = <&vd_input>;*/
+ dsi_out_port: endpoint {
+ /*remote-endpoint = <&panel_dsi_port>;*/
};
};
+
+ mipi_panel: panel@0 {
+ /*compatible = "";*/
+ status = "disabled";
+ };
+ };
+
+ hdmi: hdmi@29590000 {
+ compatible = "rockchip,rk3036-inno-hdmi";
+ reg = <0x29590000 0x4000>;
+ /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
+ /*clocks = <&cru PCLK_HDMI>;*/
+ /*clock-names = "pclk";*/
+ /*pinctrl-names = "default";*/
+ /*pinctrl-0 = <&hdmi_ctl>;*/
+ status = "disabled";
+ clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
+ <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
+ <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>;
+ clock-names = "sysclk",
+ "mclk",
+ "bclk";
+ resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
+ reset-names = "hdmi_tx";
+
+ hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ hdmi_in_lcdc: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dc_out_dpi0>;
+ };
+ };
};
sound_pwmdac: snd-card_pwmdac {
sound-dai = <&pwmdac_codec>;
};
};
+
+ co_process: e24@0 {
+ compatible = "starfive,e24";
+ reg = <0x0 0xc0110000 0x0 0x00001000
+ 0x0 0xc0111000 0x0 0x0001f000>;
+ reg-names = "ecmd","espace";
+ clocks = <&clkgen JH7110_E2_RTC_CLK>,
+ <&clkgen JH7110_E2_CLK_CORE>,
+ <&clkgen JH7110_E2_CLK_DBG>;
+ clock-names = "clk_rtc","clk_core","clk_dbg";
+ resets = <&rstgen RSTN_U0_E24_CORE>;
+ reset-names = "e24_core";
+ starfive,stg-syscon = <&stg_syscon>;
+ interrupt-parent = <&plic>;
+ firmware-name = "e24_elf";
+ irq-mode = <1>;
+ mbox-names = "tx", "rx";
+ mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
+ status = "disabled";
+ dsp@0 {};
+ };
};
};
projects / platform / kernel / linux-starfive.git / blobdiff