reg = <0x0 0x1600C000 0x0 0x4000>;
clocks = <&clkgen JH7110_SEC_HCLK>,
<&clkgen JH7110_SEC_MISCAHB_CLK>;
- clock-names = "hclk", "miscahb_clk";
+ clock-names = "hclk", "ahb";
resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
interrupts = <30>;
status = "disabled";