opp-shared;
opp-375000000 {
opp-hz = /bits/ 64 <375000000>;
- opp-microvolt = <880000>;
+ opp-microvolt = <800000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <880000>;
- };
- opp-625000000 {
- opp-hz = /bits/ 64 <625000000>;
- opp-microvolt = <880000>;
+ opp-microvolt = <800000>;
};
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
- opp-microvolt = <880000>;
- };
- opp-875000000 {
- opp-hz = /bits/ 64 <875000000>;
- opp-microvolt = <880000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <900000>;
- };
- opp-1250000000 {
- opp-hz = /bits/ 64 <1250000000>;
- opp-microvolt = <950000>;
- };
- opp-1375000000 {
- opp-hz = /bits/ 64 <1375000000>;
- opp-microvolt = <1000000>;
+ opp-microvolt = <800000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <1100000>;
- };
- opp-1625000000 {
- opp-hz = /bits/ 64 <1625000000>;
- opp-microvolt = <1100000>;
- };
- opp-1750000000 {
- opp-hz = /bits/ 64 <1750000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1040000>;
};
};
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
- cpu-idle-states = <&CPU_NONRET_0_0>;
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imac";
tlb-split;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
- cpu-idle-states = <&CPU_NONRET_0_0>;
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdc";
tlb-split;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
- cpu-idle-states = <&CPU_NONRET_0_0>;
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdc";
tlb-split;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
- cpu-idle-states = <&CPU_NONRET_0_0>;
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdc";
tlb-split;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
- cpu-idle-states = <&CPU_NONRET_0_0>;
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdc";
tlb-split;
};
};
- idle-states {
- CPU_NONRET_0_0: cpu-nonretentive-0-0 {
- compatible = "riscv,idle-state";
- riscv,sbi-suspend-param = <0x80000000>;
- entry-latency-us = <600>;
- exit-latency-us = <1100>;
- min-residency-us = <2700>;
- wakeup-latency-us = <1500>;
- };
- };
-
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#size-cells = <0>;
reg = <0x0 0x13010000 0x0 0x10000
0x0 0x21000000 0x0 0x400000>;
- clocks = <&clkgen JH7110_QSPI_CLK_REF>;
- clock-names = "clk_ref";
+ interrupts = <25>;
+ clocks = <&clkgen JH7110_QSPI_CLK_REF>,
+ <&clkgen JH7110_QSPI_CLK_APB>,
+ <&clkgen JH7110_AHB1>,
+ <&clkgen JH7110_QSPI_CLK_AHB>;
+ clock-names = "clk_ref",
+ "clk_apb",
+ "ahb1",
+ "clk_ahb";
resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
<&rstgen RSTN_U0_CDNS_QSPI_AHB>,
<&rstgen RSTN_U0_CDNS_QSPI_REF>;
resets-names = "rst_apb", "rst_ahb", "rst_ref";
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
spi-max-frequency = <250000000>;
nor_flash: nor-flash@0 {
compatible = "jedec,spi-nor";
reg=<0>;
+ cdns,read-delay = <5>;
spi-max-frequency = <100000000>;
cdns,tshsl-ns = <1>;
cdns,tsd2d-ns = <1>;
cdns,tchsh-ns = <1>;
cdns,tslch-ns = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spl@0 {
+ reg = <0x0 0x20000>;
+ };
+ uboot@100000 {
+ reg = <0x100000 0x300000>;
+ };
+ data@f00000 {
+ reg = <0xf00000 0x100000>;
+ };
+ };
};
};
compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
reg = <0x0 0x16050000 0x0 0x10000>;
clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
- <&clkgen JH7110_DMA1P_CLK_AHB>;
- clock-names = "core-clk", "cfgr-clk";
+ <&clkgen JH7110_DMA1P_CLK_AHB>,
+ <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>;
+ clock-names = "core-clk", "cfgr-clk", "stg_clk";
resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
- <&rstgen RSTN_U0_DW_DMA1P_AHB>;
- reset-names = "rst_axi", "rst_ahb";
+ <&rstgen RSTN_U0_DW_DMA1P_AHB>,
+ <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
+ reset-names = "rst_axi", "rst_ahb", "rst_stg";
interrupts = <73>;
#dma-cells = <2>;
dma-channels = <4>;
fifo-depth = <32>;
fifo-watermark-aligned;
data-addr = <0>;
+ starfive,sys-syscon = <&sys_syscon 0x9c 0x1 0x3e>;
status = "disabled";
};
<&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
<&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
<&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
- <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
- <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
+ <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
"clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
"clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
"clk_pixel_clk_if1", "clk_pixel_clk_if2",
"clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
"clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
- "clk_ispcore_2x", "clk_isp_axi", "clk_noc_bus_clk_isp_axi";
+ "clk_ispcore_2x", "clk_isp_axi";
resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
<&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
<&rstgen RSTN_U0_VIN_N_PCLK>,
compatible = "img-gpu";
reg = <0x0 0x18000000 0x0 0x100000>,
<0x0 0x130C000 0x0 0x10000>;
- clocks = <&clkgen JH7110_GPU_CORE>,
+ clocks = <&clkgen JH7110_GPU_CORE>,
<&clkgen JH7110_GPU_CLK_APB>,
<&clkgen JH7110_GPU_RTC_TOGGLE>,
<&clkgen JH7110_GPU_CORE_CLK>,
0x9 0x40000000 0x0 0x10000000>;
reg-names = "reg", "config";
device_type = "pci";
- starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
+ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
<0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
0x9 0xc0000000 0x0 0x10000000>;
reg-names = "reg", "config";
device_type = "pci";
- starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
+ starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
<0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
<0x0 0x17030000 0x0 0x1000>;
interrupts = <95>;
status = "disabled";
- clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
- <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
- <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
- <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
- <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
- <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
- <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
- <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
- <&clkgen JH7110_VOUT_SRC>,
- <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
- <&clkgen JH7110_AHB1>,
- <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
- <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
- <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
- <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
- <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
- <&clkvout JH7110_U0_DC8200_CLK_AXI>,
- <&clkvout JH7110_U0_DC8200_CLK_CORE>,
- <&clkvout JH7110_U0_DC8200_CLK_AHB>,
- <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
- <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
- <&hdmitx0_pixelclk>,
- <&clkvout JH7110_DC8200_PIX0>,
- <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
- <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
- clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
- "noc_disp","noc_isp","noc_stg","vout_src",
- "top_vout_axi","ahb1","top_vout_ahb",
- "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
- "axi_clk","core_clk","vout_ahb",
- "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
- "dc8200_pix0_out","dc8200_pix1_out";
+ clocks = <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
+ <&clkgen JH7110_VOUT_SRC>,
+ <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
+ <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
+ <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
+ <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
+ <&clkvout JH7110_U0_DC8200_CLK_AXI>,
+ <&clkvout JH7110_U0_DC8200_CLK_CORE>,
+ <&clkvout JH7110_U0_DC8200_CLK_AHB>,
+ <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
+ <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
+ <&hdmitx0_pixelclk>,
+ <&clkvout JH7110_DC8200_PIX0>,
+ <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
+ <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
+ clock-names = "noc_disp","vout_src",
+ "top_vout_axi","top_vout_ahb",
+ "pix_clk","vout_pix1",
+ "axi_clk","core_clk","vout_ahb",
+ "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
+ "dc8200_pix0_out","dc8200_pix1_out";
resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
<&rstgen RSTN_U0_DC8200_AXI>,
<&rstgen RSTN_U0_DC8200_AHB>,
<&rstgen RSTN_U0_DC8200_CORE>,
- <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
- <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
- <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
- <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
- <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
+ <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>;
reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
- "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
- "rst_noc_disp","rst_noc_stg";
- power-domains = <&pwrc JH7110_PD_VOUT>;
+ "rst_noc_disp";
};
dsi_output: dsi-output {
<&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
<&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
<&hdmitx0_pixelclk>;
- clock-names = "sysclk", "mclk", "bclk", "pclk";
+ clock-names = "sysclk", "mclk","bclk","pclk";
resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
reset-names = "hdmi_tx";
#sound-dai-cells = <0>;
};
- sound: snd-card {
+ sound0: snd-card0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Starfive-AC108-Sound-Card";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sound1: snd-card1 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Starfive-HDMI-Sound-Card";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sound2: snd-card2 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Starfive-PDM-Sound-Card";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sound3: snd-card3 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Starfive-PWMDAC-Sound-Card";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sound4: snd-card4 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Starfive-SPDIF-Sound-Card";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sound5: snd-card5 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Starfive-TDM-Sound-Card";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sound6: snd-card6 {
compatible = "simple-audio-card";
- simple-audio-card,name = "Starfive-Multi-Sound-Card";
+ simple-audio-card,name = "Starfive-WM8960-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
};
starfive_cpufreq: starfive,jh7110-cpufreq {
compatible = "starfive,jh7110-cpufreq";
- clocks = <&clkgen JH7110_PLL0_OUT>,
- <&clkgen JH7110_CPU_ROOT>,
- <&osc>;
- clock-names = "pll0", "cpu_clk", "osc";
+ clocks = <&clkgen JH7110_CPU_CORE>;
+ clock-names = "cpu_clk";
};
};
};
projects / platform / kernel / linux-starfive.git / blobdiff