RISC-V: Add StarFive JH7100 audio reset node

[platform/kernel/linux-starfive.git] / arch / riscv / boot / dts / starfive / jh7100.dtsi

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 0004474..9f387fd 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -111,6 +111,7 @@
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&plic>;
+               dma-noncoherent;
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
@@ -118,21 +119,37 @@
                clint: clint@2000000 {
                        compatible = "starfive,jh7100-clint", "sifive,clint0";
                        reg = <0x0 0x2000000 0x0 0x10000>;
-                       interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
-                                              &cpu1_intc 3 &cpu1_intc 7>;
+                       interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+                                             <&cpu1_intc 3>, <&cpu1_intc 7>;
                };
 
                plic: interrupt-controller@c000000 {
                        compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
                        reg = <0x0 0xc000000 0x0 0x4000000>;
-                       interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
-                                              &cpu1_intc 11 &cpu1_intc 9>;
+                       interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+                                             <&cpu1_intc 11>, <&cpu1_intc 9>;
                        interrupt-controller;
                        #address-cells = <0>;
                        #interrupt-cells = <1>;
                        riscv,ndev = <133>;
                };
 
+               audclk: clock-controller@10480000 {
+                       compatible = "starfive,jh7100-audclk";
+                       reg = <0x0 0x10480000 0x0 0x10000>;
+                       clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
+                                <&clkgen JH7100_CLK_AUDIO_12288>,
+                                <&clkgen JH7100_CLK_DOM7AHB_BUS>;
+                       clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
+                       #clock-cells = <1>;
+               };
+
+               audrst: reset-controller@10490000 {
+                       compatible = "starfive,jh7100-audrst";
+                       reg = <0x0 0x10490000 0x0 0x10000>;
+                       #reset-cells = <1>;
+               };
+
                clkgen: clock-controller@11800000 {
                        compatible = "starfive,jh7100-clkgen";
                        reg = <0x0 0x11800000 0x0 0x10000>;