Merge patch series "riscv, mm: detect svnapot cpu support at runtime"

[platform/kernel/linux-starfive.git] / arch / riscv / Kconfig

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c5e42cc..c736dc8 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -44,7 +44,7 @@ config RISCV
        select ARCH_USE_QUEUED_RWLOCKS
        select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
        select ARCH_WANT_FRAME_POINTERS
-       select ARCH_WANT_GENERAL_HUGETLB
+       select ARCH_WANT_GENERAL_HUGETLB if !RISCV_ISA_SVNAPOT
        select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
        select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
        select ARCH_WANT_LD_ORPHAN_WARN if !XIP_KERNEL
@@ -398,6 +398,25 @@ config RISCV_ISA_C
 
          If you don't know what to do here, say Y.
 
+config RISCV_ISA_SVNAPOT
+       bool "SVNAPOT extension support"
+       depends on 64BIT && MMU
+       default y
+       select RISCV_ALTERNATIVE
+       help
+         Allow kernel to detect the SVNAPOT ISA-extension dynamically at boot
+         time and enable its usage.
+
+         The SVNAPOT extension is used to mark contiguous PTEs as a range
+         of contiguous virtual-to-physical translations for a naturally
+         aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
+         size. When HUGETLBFS is also selected this option unconditionally
+         allocates some memory for each NAPOT page size supported by the kernel.
+         When optimizing for low memory consumption and for platforms without
+         the SVNAPOT extension, it may be better to say N here.
+
+         If you don't know what to do here, say Y.
+
 config RISCV_ISA_SVPBMT
        bool "SVPBMT extension support"
        depends on 64BIT && MMU