RISC-V: align ISA extension Kconfig help text with each other

[platform/kernel/linux-starfive.git] / arch / riscv / Kconfig

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d7252ce..ba94d08 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -33,6 +33,7 @@ config RISCV
        select ARCH_HAS_STRICT_MODULE_RWX if MMU && !XIP_KERNEL
        select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
        select ARCH_HAS_UBSAN_SANITIZE_ALL
+       select ARCH_HAS_VDSO_DATA
        select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
        select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
        select ARCH_STACKWALK
@@ -127,6 +128,7 @@ config RISCV
        select OF_IRQ
        select PCI_DOMAINS_GENERIC if PCI
        select PCI_MSI if PCI
+       select RISCV_ALTERNATIVE if !XIP_KERNEL
        select RISCV_INTC
        select RISCV_TIMER if RISCV_SBI
        select SIFIVE_PLIC
@@ -178,8 +180,8 @@ config MMU
 
 config PAGE_OFFSET
        hex
-       default 0xC0000000 if 32BIT
-       default 0x80000000 if 64BIT && !MMU
+       default 0xC0000000 if 32BIT && MMU
+       default 0x80000000 if !MMU
        default 0xff60000000000000 if 64BIT
 
 config KASAN_SHADOW_OFFSET
@@ -280,7 +282,6 @@ config ARCH_RV32I
        select GENERIC_LIB_ASHRDI3
        select GENERIC_LIB_LSHRDI3
        select GENERIC_LIB_UCMPDI2
-       select MMU
 
 config ARCH_RV64I
        bool "RV64I"
@@ -321,6 +322,14 @@ config SMP
 
          If you don't know what to do here, say N.
 
+config SCHED_MC
+       bool "Multi-core scheduler support"
+       depends on SMP
+       help
+         Multi-core scheduler support improves the CPU scheduler's decision
+         making when dealing with multi-core CPU chips at a cost of slightly
+         increased overhead in some places. If unsure say N here.
+
 config NR_CPUS
        int "Maximum number of CPUs (2-512)"
        depends on SMP
@@ -400,32 +409,31 @@ config RISCV_ISA_C
          If you don't know what to do here, say Y.
 
 config RISCV_ISA_SVNAPOT
-       bool "SVNAPOT extension support"
+       bool "Svnapot extension support for supervisor mode NAPOT pages"
        depends on 64BIT && MMU
+       depends on RISCV_ALTERNATIVE
        default y
-       select RISCV_ALTERNATIVE
        help
-         Allow kernel to detect the SVNAPOT ISA-extension dynamically at boot
+         Allow kernel to detect the Svnapot ISA-extension dynamically at boot
          time and enable its usage.
 
-         The SVNAPOT extension is used to mark contiguous PTEs as a range
+         The Svnapot extension is used to mark contiguous PTEs as a range
          of contiguous virtual-to-physical translations for a naturally
          aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
          size. When HUGETLBFS is also selected this option unconditionally
          allocates some memory for each NAPOT page size supported by the kernel.
          When optimizing for low memory consumption and for platforms without
-         the SVNAPOT extension, it may be better to say N here.
+         the Svnapot extension, it may be better to say N here.
 
          If you don't know what to do here, say Y.
 
 config RISCV_ISA_SVPBMT
-       bool "SVPBMT extension support"
+       bool "Svpbmt extension support for supervisor mode page-based memory types"
        depends on 64BIT && MMU
-       depends on !XIP_KERNEL
+       depends on RISCV_ALTERNATIVE
        default y
-       select RISCV_ALTERNATIVE
        help
-          Adds support to dynamically detect the presence of the SVPBMT
+          Adds support to dynamically detect the presence of the Svpbmt
           ISA-extension (Supervisor-mode: page-based memory types) and
           enable its usage.
 
@@ -433,7 +441,7 @@ config RISCV_ISA_SVPBMT
           that indicate the cacheability, idempotency, and ordering
           properties for access to that page.
 
-          The SVPBMT extension is only available on 64Bit cpus.
+          The Svpbmt extension is only available on 64-bit cpus.
 
           If you don't know what to do here, say Y.
 
@@ -448,8 +456,8 @@ config TOOLCHAIN_HAS_ZBB
 config RISCV_ISA_ZBB
        bool "Zbb extension support for bit manipulation instructions"
        depends on TOOLCHAIN_HAS_ZBB
-       depends on !XIP_KERNEL && MMU
-       select RISCV_ALTERNATIVE
+       depends on MMU
+       depends on RISCV_ALTERNATIVE
        default y
        help
           Adds support to dynamically detect the presence of the ZBB
@@ -463,9 +471,9 @@ config RISCV_ISA_ZBB
 
 config RISCV_ISA_ZICBOM
        bool "Zicbom extension support for non-coherent DMA operation"
-       depends on !XIP_KERNEL && MMU
+       depends on MMU
+       depends on RISCV_ALTERNATIVE
        default y
-       select RISCV_ALTERNATIVE
        select RISCV_DMA_NONCOHERENT
        help
           Adds support to dynamically detect the presence of the ZICBOM
@@ -479,11 +487,11 @@ config RISCV_ISA_ZICBOM
 
 config RISCV_ISA_ZICBOZ
        bool "Zicboz extension support for faster zeroing of memory"
-       depends on !XIP_KERNEL && MMU
-       select RISCV_ALTERNATIVE
+       depends on MMU
+       depends on RISCV_ALTERNATIVE
        default y
        help
-          Enable the use of the ZICBOZ extension (cbo.zero instruction)
+          Enable the use of the Zicboz extension (cbo.zero instruction)
           when available.
 
           The Zicboz extension is used for faster zeroing of memory.