config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
-config TARGET_SIFIVE_FU540
- bool "Support SiFive FU540 Board"
+config TARGET_SIFIVE_UNLEASHED
+ bool "Support SiFive Unleashed Board"
+
+config TARGET_SIFIVE_UNMATCHED
+ bool "Support SiFive Unmatched Board"
+ select SYS_CACHE_SHIFT_6
+
+config TARGET_SIPEED_MAIX
+ bool "Support Sipeed Maix Board"
+ select SYS_CACHE_SHIFT_6
+
+config TARGET_OPENPITON_RISCV64
+ bool "Support RISC-V cores on OpenPiton SoC"
endchoice
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
-source "board/sifive/fu540/Kconfig"
+source "board/sifive/unleashed/Kconfig"
+source "board/sifive/unmatched/Kconfig"
+source "board/openpiton/riscv64/Kconfig"
+source "board/sipeed/maix/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
+source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
# architecture-specific options below
config 64BIT
bool
+config DMA_ADDR_T_64BIT
+ bool
+ default y if 64BIT
+
config SIFIVE_CLINT
bool
- depends on RISCV_MMODE || SPL_RISCV_MMODE
- select REGMAP
- select SYSCON
- select SPL_REGMAP if SPL
- select SPL_SYSCON if SPL
+ depends on RISCV_MMODE
help
The SiFive CLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
-config ANDES_PLIC
+config SPL_SIFIVE_CLINT
bool
- depends on RISCV_MMODE || SPL_RISCV_MMODE
- select REGMAP
- select SYSCON
- select SPL_REGMAP if SPL
- select SPL_SYSCON if SPL
+ depends on SPL_RISCV_MMODE
help
- The Andes PLIC block holds memory-mapped claim and pending registers
- associated with software interrupt.
+ The SiFive CLINT block holds memory-mapped control and status registers
+ associated with software and timer interrupts.
-config ANDES_PLMT
+config ANDES_PLIC
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SPL_REGMAP if SPL
select SPL_SYSCON if SPL
help
- The Andes PLMT block holds memory-mapped mtime register
- associated with timer tick.
-
-config RISCV_RDTIME
- bool
- default y if RISCV_SMODE || SPL_RISCV_SMODE
- help
- The provides the riscv_get_time() API that is implemented using the
- standard rdtime instruction. This is the case for S-mode U-Boot, and
- is useful for processors that support rdtime in M-mode too.
+ The Andes PLIC block holds memory-mapped claim and pending registers
+ associated with software interrupt.
config SYS_MALLOC_F_LEN
default 0x1000
config SHOW_REGS
bool "Show registers on unhandled exception"
+config RISCV_PRIV_1_9
+ bool "Use version 1.9 of the RISC-V priviledged specification"
+ help
+ Older versions of the RISC-V priviledged specification had
+ separate counter enable CSRs for each privilege mode. Writing
+ to the unified mcounteren CSR on a processor implementing the
+ old specification will result in an illegal instruction
+ exception. In addition to counter CSR changes, the way virtual
+ memory is configured was also changed.
+
config STACK_SIZE_SHIFT
int
default 14
+config OF_BOARD_FIXUP
+ default y if OF_SEPARATE && RISCV_SMODE
+
+menu "Use assembly optimized implementation of memory routines"
+
+config USE_ARCH_MEMCPY
+ bool "Use an assembly optimized implementation of memcpy"
+ default y
+ help
+ Enable the generation of an optimized version of memcpy.
+ Such an implementation may be faster under some conditions
+ but may increase the binary size.
+
+config SPL_USE_ARCH_MEMCPY
+ bool "Use an assembly optimized implementation of memcpy for SPL"
+ default y if USE_ARCH_MEMCPY
+ depends on SPL
+ help
+ Enable the generation of an optimized version of memcpy.
+ Such an implementation may be faster under some conditions
+ but may increase the binary size.
+
+config TPL_USE_ARCH_MEMCPY
+ bool "Use an assembly optimized implementation of memcpy for TPL"
+ default y if USE_ARCH_MEMCPY
+ depends on TPL
+ help
+ Enable the generation of an optimized version of memcpy.
+ Such an implementation may be faster under some conditions
+ but may increase the binary size.
+
+config USE_ARCH_MEMMOVE
+ bool "Use an assembly optimized implementation of memmove"
+ default y
+ help
+ Enable the generation of an optimized version of memmove.
+ Such an implementation may be faster under some conditions
+ but may increase the binary size.
+
+config SPL_USE_ARCH_MEMMOVE
+ bool "Use an assembly optimized implementation of memmove for SPL"
+ default y if USE_ARCH_MEMCPY
+ depends on SPL
+ help
+ Enable the generation of an optimized version of memmove.
+ Such an implementation may be faster under some conditions
+ but may increase the binary size.
+
+config TPL_USE_ARCH_MEMMOVE
+ bool "Use an assembly optimized implementation of memmove for TPL"
+ default y if USE_ARCH_MEMCPY
+ depends on TPL
+ help
+ Enable the generation of an optimized version of memmove.
+ Such an implementation may be faster under some conditions
+ but may increase the binary size.
+
+config USE_ARCH_MEMSET
+ bool "Use an assembly optimized implementation of memset"
+ default y
+ help
+ Enable the generation of an optimized version of memset.
+ Such an implementation may be faster under some conditions
+ but may increase the binary size.
+
+config SPL_USE_ARCH_MEMSET
+ bool "Use an assembly optimized implementation of memset for SPL"
+ default y if USE_ARCH_MEMSET
+ depends on SPL
+ help
+ Enable the generation of an optimized version of memset.
+ Such an implementation may be faster under some conditions
+ but may increase the binary size.
+
+config TPL_USE_ARCH_MEMSET
+ bool "Use an assembly optimized implementation of memset for TPL"
+ default y if USE_ARCH_MEMSET
+ depends on TPL
+ help
+ Enable the generation of an optimized version of memset.
+ Such an implementation may be faster under some conditions
+ but may increase the binary size.
+
+endmenu
+
endmenu
projects / platform / kernel / u-boot.git / blobdiff