Merge branch '2020-07-01-kconfig-etc-updates' into next

[platform/kernel/u-boot.git] / arch / riscv / Kconfig

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 5ef6849..5d01f40 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT
 config TARGET_SIFIVE_FU540
        bool "Support SiFive FU540 Board"
 
+config TARGET_SIPEED_MAIX
+       bool "Support Sipeed Maix Board"
+
 endchoice
 
 config SYS_ICACHE_OFF
@@ -53,9 +56,11 @@ source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/fu540/Kconfig"
+source "board/sipeed/maix/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
+source "arch/riscv/cpu/fu540/Kconfig"
 source "arch/riscv/cpu/generic/Kconfig"
 
 # architecture-specific options below
@@ -193,6 +198,7 @@ config SYS_MALLOC_F_LEN
 
 config SMP
        bool "Symmetric Multi-Processing"
+       depends on SBI_V01 || !RISCV_SMODE
        help
          This enables support for systems with more than one CPU. If
          you say N here, U-Boot will run on single and multiprocessor
@@ -225,14 +231,32 @@ config SBI
        bool
        default y if RISCV_SMODE || SPL_RISCV_SMODE
 
+choice
+       prompt "SBI support"
+       default SBI_V02
+
 config SBI_V01
        bool "SBI v0.1 support"
-       default y
        depends on SBI
        help
          This config allows kernel to use SBI v0.1 APIs. This will be
          deprecated in future once legacy M-mode software are no longer in use.
 
+config SBI_V02
+       bool "SBI v0.2 support"
+       depends on SBI
+       help
+         This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
+         scalable and extendable to handle future needs for RISC-V supervisor
+         interfaces. For example, with SBI v0.2 HSM extension, only a single
+         hart need to boot and enter operating system. The booting hart can
+         bring up secondary harts one by one afterwards.
+
+         Choose this option if OpenSBI v0.7 or above release is used together
+         with U-Boot.
+
+endchoice
+
 config SBI_IPI
        bool
        depends on SBI
@@ -249,6 +273,16 @@ config XIP
 config SHOW_REGS
        bool "Show registers on unhandled exception"
 
+config RISCV_PRIV_1_9
+       bool "Use version 1.9 of the RISC-V priviledged specification"
+       help
+         Older versions of the RISC-V priviledged specification had
+         separate counter enable CSRs for each privilege mode. Writing
+         to the unified mcounteren CSR on a processor implementing the
+         old specification will result in an illegal instruction
+         exception. In addition to counter CSR changes, the way virtual
+         memory is configured was also changed.
+
 config STACK_SIZE_SHIFT
        int
        default 14