prompt "Target select"
optional
-config TARGET_AX25_AE350
- bool "Support ax25-ae350"
+config TARGET_AE350
+ bool "Support ae350"
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
+ select BOARD_LATE_INIT
config TARGET_SIFIVE_UNLEASHED
bool "Support SiFive Unleashed Board"
bool "Support SiFive Unmatched Board"
select SYS_CACHE_SHIFT_6
+config TARGET_STARFIVE_VISIONFIVE2
+ bool "Support StarFive VisionFive2 Board"
+ select BOARD_LATE_INIT
+
+config TARGET_TH1520_LPI4A
+ bool "Support Sipeed's TH1520 Lichee PI 4A Board"
+ select SYS_CACHE_SHIFT_6
+
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
select SYS_CACHE_SHIFT_6
help
Do not enable data cache in SPL.
+config SPL_ZERO_MEM_BEFORE_USE
+ bool "Zero memory before use"
+ depends on SPL
+ default n
+ help
+ Zero stack/GD/malloc area in SPL before using them, this is needed for
+ Sifive core devices that uses L2 cache to store SPL.
+
# board-specific options below
-source "board/AndesTech/ax25-ae350/Kconfig"
+source "board/AndesTech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
+source "board/thead/th1520_lpi4a/Kconfig"
source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
+source "board/starfive/visionfive2/Kconfig"
# platform-specific options below
-source "arch/riscv/cpu/ax25/Kconfig"
+source "arch/riscv/cpu/andesv5/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
+source "arch/riscv/cpu/jh7110/Kconfig"
# architecture-specific options below
when building U-Boot, which results in compressed instructions in the
U-Boot binary.
+config RISCV_ISA_F
+ bool "Standard extension for Single-Precision Floating Point"
+ default y
+ help
+ Adds "F" to the ISA string passed to the compiler.
+
+config RISCV_ISA_D
+ bool "Standard extension for Double-Precision Floating Point"
+ depends on RISCV_ISA_F
+ default y
+ help
+ Adds "D" to the ISA string passed to the compiler and changes the
+ riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
+ lp64d.
+
config RISCV_ISA_A
def_bool y
bool
default y if 64BIT
-config SIFIVE_CLINT
+config RISCV_ACLINT
bool
depends on RISCV_MMODE
+ select REGMAP
+ select SYSCON
help
- The SiFive CLINT block holds memory-mapped control and status registers
+ The RISC-V ACLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
-config SPL_SIFIVE_CLINT
+config SPL_RISCV_ACLINT
bool
depends on SPL_RISCV_MMODE
+ select SPL_REGMAP
+ select SPL_SYSCON
help
- The SiFive CLINT block holds memory-mapped control and status registers
+ The RISC-V ACLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
config SIFIVE_CACHE
help
This enables the operations to configure SiFive cache
-config ANDES_PLIC
+config ANDES_PLICSW
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SPL_REGMAP if SPL
select SPL_SYSCON if SPL
help
- The Andes PLIC block holds memory-mapped claim and pending registers
- associated with software interrupt.
-
-config SYS_MALLOC_F_LEN
- default 0x1000
+ The Andes PLICSW block holds memory-mapped claim and pending
+ registers associated with software interrupt.
config SMP
bool "Symmetric Multi-Processing"
deprecated in future once legacy M-mode software are no longer in use.
config SBI_V02
- bool "SBI v0.2 support"
+ bool "SBI v0.2 or later support"
depends on SBI
help
- This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
- scalable and extendable to handle future needs for RISC-V supervisor
- interfaces. For example, with SBI v0.2 HSM extension, only a single
- hart need to boot and enter operating system. The booting hart can
- bring up secondary harts one by one afterwards.
+ The SBI specification introduced the concept of extensions in version
+ v0.2. With this configuration option U-Boot can detect and use SBI
+ extensions. With the HSM extension introduced in SBI 0.2, only a
+ single hart needs to boot and enter the operating system. The booting
+ hart can bring up secondary harts one by one afterwards.
- Choose this option if OpenSBI v0.7 or above release is used together
+ Choose this option if OpenSBI release v0.7 or above is used together
with U-Boot.
endchoice
from a NOR flash memory without copying the code to ram.
Say yes here if U-Boot boots from flash directly.
+config SPL_XIP
+ bool "Enable XIP mode for SPL"
+ help
+ If SPL starts in read-only memory (XIP for example) then we shouldn't
+ rely on lock variables (for example hart_lottery and available_harts_lock),
+ this affects only SPL, other stages should proceed as non-XIP.
+
+config AVAILABLE_HARTS
+ bool "Send IPI by available harts"
+ default y
+ help
+ By default, IPI sending mechanism will depend on available_harts.
+ If disable this, it will send IPI by CPUs node numbers of device tree.
+
config SHOW_REGS
bool "Show registers on unhandled exception"
projects / platform / kernel / u-boot.git / blobdiff