#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
+#include <asm/msi_bitmap.h>
#include <asm/ppc-pci.h>
#include <asm/opal.h>
#include <asm/iommu.h>
struct pci_controller *hose = pci_bus_to_host(pdev->bus);
struct pnv_phb *phb = hose->private_data;
- return (phb && phb->msi_map) ? 0 : -ENODEV;
-}
-
-static unsigned int pnv_get_one_msi(struct pnv_phb *phb)
-{
- unsigned long flags;
- unsigned int id, rc;
-
- spin_lock_irqsave(&phb->lock, flags);
-
- id = find_next_zero_bit(phb->msi_map, phb->msi_count, phb->msi_next);
- if (id >= phb->msi_count && phb->msi_next)
- id = find_next_zero_bit(phb->msi_map, phb->msi_count, 0);
- if (id >= phb->msi_count) {
- rc = 0;
- goto out;
- }
- __set_bit(id, phb->msi_map);
- rc = id + phb->msi_base;
-out:
- spin_unlock_irqrestore(&phb->lock, flags);
- return rc;
-}
-
-static void pnv_put_msi(struct pnv_phb *phb, unsigned int hwirq)
-{
- unsigned long flags;
- unsigned int id;
-
- if (WARN_ON(hwirq < phb->msi_base ||
- hwirq >= (phb->msi_base + phb->msi_count)))
- return;
- id = hwirq - phb->msi_base;
-
- spin_lock_irqsave(&phb->lock, flags);
- __clear_bit(id, phb->msi_map);
- spin_unlock_irqrestore(&phb->lock, flags);
+ return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
}
static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
struct pnv_phb *phb = hose->private_data;
struct msi_desc *entry;
struct msi_msg msg;
- unsigned int hwirq, virq;
+ int hwirq;
+ unsigned int virq;
int rc;
if (WARN_ON(!phb))
pci_name(pdev));
return -ENXIO;
}
- hwirq = pnv_get_one_msi(phb);
- if (!hwirq) {
+ hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
+ if (hwirq < 0) {
pr_warn("%s: Failed to find a free MSI\n",
pci_name(pdev));
return -ENOSPC;
}
- virq = irq_create_mapping(NULL, hwirq);
+ virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
if (virq == NO_IRQ) {
pr_warn("%s: Failed to map MSI to linux irq\n",
pci_name(pdev));
- pnv_put_msi(phb, hwirq);
+ msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
return -ENOMEM;
}
- rc = phb->msi_setup(phb, pdev, hwirq, entry->msi_attrib.is_64,
- &msg);
+ rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
+ virq, entry->msi_attrib.is_64, &msg);
if (rc) {
pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
irq_dispose_mapping(virq);
- pnv_put_msi(phb, hwirq);
+ msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
return rc;
}
irq_set_msi_desc(virq, entry);
if (entry->irq == NO_IRQ)
continue;
irq_set_msi_desc(entry->irq, NULL);
- pnv_put_msi(phb, virq_to_hw(entry->irq));
+ msi_bitmap_free_hwirqs(&phb->msi_bmp,
+ virq_to_hw(entry->irq) - phb->msi_base, 1);
irq_dispose_mapping(entry->irq);
}
}
.write = pnv_pci_write_config,
};
-
-static void pnv_tce_invalidate(struct iommu_table *tbl,
- u64 *startp, u64 *endp)
-{
- u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
- unsigned long start, end, inc;
-
- start = __pa(startp);
- end = __pa(endp);
-
-
- /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
- if (tbl->it_busno) {
- start <<= 12;
- end <<= 12;
- inc = 128 << 12;
- start |= tbl->it_busno;
- end |= tbl->it_busno;
- }
- /* p7ioc-style invalidation, 2 TCEs per write */
- else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
- start |= (1ull << 63);
- end |= (1ull << 63);
- inc = 16;
- }
- /* Default (older HW) */
- else
- inc = 128;
-
- end |= inc - 1; /* round up end to be different than start */
-
- mb(); /* Ensure above stores are visible */
- while (start <= end) {
- __raw_writeq(start, invalidate);
- start += inc;
- }
- /* The iommu layer will do another mb() for us on build() and
- * we don't care on free()
- */
-}
-
-
static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
unsigned long uaddr, enum dma_data_direction direction,
struct dma_attrs *attrs)
* of flags if that becomes the case
*/
if (tbl->it_type & TCE_PCI_SWINV_CREATE)
- pnv_tce_invalidate(tbl, tces, tcep - 1);
+ pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
return 0;
}
while (npages--)
*(tcep++) = 0;
- if (tbl->it_type & TCE_PCI_SWINV_FREE)
- pnv_tce_invalidate(tbl, tces, tcep - 1);
+ if (tbl->it_type & TCE_PCI_SWINV_CREATE)
+ pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
}
static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
pnv_pci_dma_fallback_setup(hose, pdev);
}
-/* Fixup wrong class code in p7ioc root complex */
+void pnv_pci_shutdown(void)
+{
+ struct pci_controller *hose;
+
+ list_for_each_entry(hose, &hose_list, list_node) {
+ struct pnv_phb *phb = hose->private_data;
+
+ if (phb && phb->shutdown)
+ phb->shutdown(phb);
+ }
+}
+
+/* Fixup wrong class code in p7ioc and p8 root complex */
static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
{
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
if (!found_ioda)
for_each_compatible_node(np, NULL, "ibm,p5ioc2")
pnv_pci_init_p5ioc2_hub(np);
+
+ /* Look for ioda2 built-in PHB3's */
+ for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
+ pnv_pci_init_ioda2_phb(np);
}
/* Setup the linkage between OF nodes and PHBs */
projects / platform / adaptation / renesas_rcar / renesas_kernel.git / blobdiff