extern int update_flash_size(int flash_size);
#endif
-#if defined(CONFIG_SC3)
-extern void sc3_read_eeprom(void);
-#endif
-
#if defined(CONFIG_CMD_DOC)
void doc_init(void);
#endif
#ifdef CONFIG_PRAM
ulong reg;
#endif
-#ifdef CONFIG_DEEP_SLEEP
- const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
- u32 start_addr;
- typedef void (*func_t)(void);
- func_t kernel_resume;
-#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
if ((*init_fnc_ptr) () != 0)
hang();
-#ifdef CONFIG_DEEP_SLEEP
- /* Jump to kernel in deep sleep case */
- if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
- l2cache_init();
-#if defined(CONFIG_RAMBOOT_PBL)
- disable_cpc_sram();
-#endif
- enable_cpc();
- start_addr = in_be32(&scfg->sparecr[1]);
- kernel_resume = (func_t)start_addr;
- kernel_resume();
- }
-#endif
-
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL));
#endif /* CONFIG_405GP, CONFIG_405EP */
#endif /* CONFIG_SYS_EXTBDINFO */
-#if defined(CONFIG_SC3)
- sc3_read_eeprom();
-#endif
-
#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
mac_read_from_eeprom();
#endif
#if defined(CONFIG_CMD_NET)
WATCHDOG_RESET();
puts("Net: ");
- eth_initialize(bd);
+ eth_initialize();
#endif
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)