#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
#define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */
+#define L1CSR2_DCSTASHID 0x000003ff /* Data Cache Stash ID */
#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
-#ifdef CONFIG_MPC8536
+#ifdef CONFIG_ARCH_MPC8536
#define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/
#else
#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
u32 soc_ver;
u32 num_cores;
u32 mask; /* which cpu(s) actually exist */
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ u32 dsp_num_cores;
+ u32 dsp_mask; /* which DSP cpu(s) actually exist */
+#endif
};
struct cpu_type *identify_cpu(u32 ver);
int fixup_cpu(void);
int fsl_qoriq_core_to_cluster(unsigned int core);
+int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
#define CPU_TYPE_ENTRY(n, v, nc) \
/* In misc.c */
void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
+int prt_83xx_rsr(void);
+int prt_8260_rsr(void);
+int prt_8260_clks(void);
+
#endif /* ndef ASSEMBLY*/
#ifdef CONFIG_MACH_SPECIFIC
-#if defined(CONFIG_8xx)
-#define _machine _MACH_8xx
-#define have_of 0
-#elif defined(CONFIG_WALNUT)
+#if defined(CONFIG_WALNUT)
#define _machine _MACH_walnut
#define have_of 0
-#elif defined(CONFIG_MPC8260)
-#define _machine _MACH_8260
-#define have_of 0
-#elif defined(CONFIG_SANDPOINT)
-#define _machine _MACH_sandpoint
#else
#error "Machine not defined correctly"
#endif