#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
+/* Memory mapped registers */
+#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+
+#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
#define SDR0_SRST0_DMC 0x00200000