powerpc/fsl-corenet: remove dead variant symbols

[platform/kernel/u-boot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 632e3c1..c2d33b1 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1,7 +1,7 @@
 /*
  * MPC85xx Internal Memory Map
  *
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
  *
  * Copyright(c) 2002,2003 Motorola Inc.
  * Xianghua Xiao (x.xiao@motorola.com)
@@ -1729,6 +1729,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR2_DTSEC2_2  0x00004000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3  0x00002000
 #define FSL_CORENET_DEVDISR2_DTSEC2_4  0x00001000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5  0x00000800
 #define FSL_CORENET_NUM_DEVDISR                2
        u8      res7[8];
        u32     powmgtcsr;      /* Power management status & control */
@@ -1758,13 +1759,14 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR5_DDR_SYNC            0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT               7
 #define FSL_CORENET_RCWSR5_SRDS_EN             0x00002000
+#define FSL_CORENET_RCWSR6_BOOT_LOC    0x0f800000
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2         0x3c000000 /* bits 162..165 */
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3         0x003c0000 /* bits 170..173 */
 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT     0x00400000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1         0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2         0x00100000
 #define FSL_CORENET_RCWSR11_EC1                        0x00c00000 /* bits 360..361 */
-#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060)
+#ifdef CONFIG_PPC_P4080
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1             0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1               0x00800000
 #define FSL_CORENET_RCWSR11_EC2                        0x001c0000 /* bits 363..365 */
@@ -1772,7 +1774,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2             0x00080000
 #define FSL_CORENET_RCWSR11_EC2_USB2                   0x00100000
 #endif
-#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \
+#if defined(CONFIG_PPC_P2041) \
        || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII       0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII         0x00800000
@@ -1934,7 +1936,11 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORPLLSR_DDR_RATIO     0x3e000000
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT       25
 #else
+#ifdef CONFIG_BSC9131
+#define MPC85xx_PORPLLSR_DDR_RATIO     0x00003f00
+#else
 #define MPC85xx_PORPLLSR_DDR_RATIO     0x00003e00
+#endif
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT       9
 #endif
 #define MPC85xx_PORPLLSR_QE_RATIO      0x3e000000
@@ -2081,6 +2087,50 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_SPI_MASK                0x00600000
 #define MPC85xx_PMUXCR_SPI             0x00000000
 #endif
+#if defined(CONFIG_BSC9131)
+#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ      0x40000000
+#define MPC85xx_PMUXCR_TSEC2_USB               0xC0000000
+#define MPC85xx_PMUXCR_TSEC2_1588_PPS          0x10000000
+#define MPC85xx_PMUXCR_TSEC2_1588_RSVD         0x30000000
+#define MPC85xx_PMUXCR_IFC_AD_GPIO             0x04000000
+#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK                0x0C000000
+#define MPC85xx_PMUXCR_IFC_AD15_GPIO           0x01000000
+#define MPC85xx_PMUXCR_IFC_AD15_TIMER2         0x02000000
+#define MPC85xx_PMUXCR_IFC_AD16_GPO8           0x00400000
+#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0                0x00800000
+#define MPC85xx_PMUXCR_IFC_AD17_GPO            0x00100000
+#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK       0x00300000
+#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP     0x00200000
+#define MPC85xx_PMUXCR_IFC_CS2_GPO65           0x00040000
+#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI         0x00080000
+#define MPC85xx_PMUXCR_SDHC_USIM               0x00010000
+#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK                0x00020000
+#define MPC85xx_PMUXCR_SDHC_GPIO77             0x00030000
+#define MPC85xx_PMUXCR_SDHC_RESV               0x00004000
+#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD                0x00008000
+#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4                0x0000C000
+#define MPC85xx_PMUXCR_USB_CLK_UART_SIN                0x00001000
+#define MPC85xx_PMUXCR_USB_CLK_GPIO69          0x00002000
+#define MPC85xx_PMUXCR_USB_CLK_TIMER3          0x00003000
+#define MPC85xx_PMUXCR_USB_UART_GPIO0          0x00000400
+#define MPC85xx_PMUXCR_USB_RSVD                        0x00000C00
+#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN      0x00000800
+#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL   0x00000100
+#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72      0x00000200
+#define MPC85xx_PMUXCR_USB_D1_2_RSVD           0x00000300
+#define MPC85xx_PMUXCR_USB_DIR_GPIO2           0x00000040
+#define MPC85xx_PMUXCR_USB_DIR_TIMER1          0x00000080
+#define MPC85xx_PMUXCR_USB_DIR_MCP_B           0x000000C0
+#define MPC85xx_PMUXCR_SPI1_UART3              0x00000010
+#define MPC85xx_PMUXCR_SPI1_SIM                        0x00000020
+#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74     0x00000030
+#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B    0x00000004
+#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen  0x00000008
+#define MPC85xx_PMUXCR_SPI1_CS2_GPO75          0x0000000C
+#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM   0x00000001
+#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen  0x00000002
+#define MPC85xx_PMUXCR_SPI1_CS3_GPO76          0x00000003
+#endif
        u32     pmuxcr2;        /* Alt. function signal multiplex control 2 */
 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
 #define MPC85xx_PMUXCR2_UART_GPIO              0x40000000
@@ -2111,7 +2161,69 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR2_ETSECUSB_MASK  0x001f8000
 #define MPC85xx_PMUXCR2_USB            0x00150000
 #endif
+#if defined(CONFIG_BSC9131)
+#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD             0X40000000
+#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS            0X80000000
+#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42             0xC0000000
+#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2               0x10000000
+#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK            0x20000000
+#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43             0x30000000
+#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD             0x04000000
+#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B           0x08000000
+#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44             0x0C000000
+#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED            0x01000000
+#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD               0x02000000
+#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45             0x03000000
+#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP                        0x00400000
+#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B            0x00800000
+#define MPC85xx_PMUXCR2_ANT1_TIMER5                    0x00100000
+#define MPC85xx_PMUXCR2_ANT1_TSEC_1588                 0x00200000
+#define MPC85xx_PMUXCR2_ANT1_GPIO95_19                 0x00300000
+#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK     0x00040000
+#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD          0x00080000
+#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20     0x000C0000
+#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0           0x00010000
+#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3          0x00020000
+#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84          0x00030000
+#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4               0x00004000
+#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7         0x00008000
+#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88          0x0000C000
+#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK                0x00001000
+#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9         0x00002000
+#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22          0x00003000
+#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7         0x00000400
+#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11     0x00000800
+#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24                0x00000C00
+#define MPC85xx_PMUXCR2_ANT2_RSVD                      0x00000100
+#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA              0x00000300
+#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB                0x00000040
+#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO       0x000000C0
+#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD                        0x00000010
+#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8              0x00000020
+#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61              0x00000030
+#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53                 0x00000004
+#define MPC85xx_PMUXCR2_ANT3_DO_TDM                    0x00000001
+#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49              0x00000002
+       u32     pmuxcr3;
+
+#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM                 0x40000000
+#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51          0x80000000
+#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B    0x10000000
+#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53          0x20000000
+#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B                 0x04000000
+#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54                        0x08000000
+#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT       0x01000000
+#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56          0x02000000
+#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT              0x00400000
+#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57               0x00800000
+#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93                 0x00100000
+#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94                 0x00040000
+#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD                  0x00010000
+#define MPC85xx_PMUXCR3_ANT2_GPO89                     0x00030000
+       u32 pmuxcr4;
+#else
        u8      res6[8];
+#endif
        u32     devdisr;        /* Device disable control */
 #define MPC85xx_DEVDISR_PCI1           0x80000000
 #define MPC85xx_DEVDISR_PCI2           0x40000000
@@ -2149,8 +2261,7 @@ typedef struct ccsr_gur {
        u8      res11a[76];
        par_io_t qe_par_io[7];
        u8      res11b[1600];
-#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-      defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
        u8      res11a[12];
        u32     iovselsr;
        u8      res11b[60];
@@ -2166,7 +2277,14 @@ typedef struct ccsr_gur {
        u32     ddrdllcr;       /* DDR DLL control */
        u8      res14[12];
        u32     lbcdllcr;       /* LBC DLL control */
+#if defined(CONFIG_BSC9131)
+       u8      res15[12];
+       u32     halt_req_mask;
+#define HALTED_TO_HALT_REQ_MASK_0      0x80000000
+       u8      res18[232];
+#else
        u8      res15[248];
+#endif
        u32     lbiuiplldcr0;   /* LBIU PLL Debug Reg 0 */
        u32     lbiuiplldcr1;   /* LBIU PLL Debug Reg 1 */
        u32     ddrioovcr;      /* DDR IO Override Control */