#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080
-#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
#define FSL_CORENET_RCWSR13_EC2 0x0c000000
#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
-#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
-#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
-#if defined(CONFIG_ARCH_BSC9132)
-#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
-#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
- (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
-#endif
-
#define CONFIG_SYS_FSL_CPC_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
#define CONFIG_SYS_FSL_SCFG_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
-#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
- (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
-#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
- (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
#define CONFIG_SYS_FSL_QMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
#define CONFIG_SYS_FSL_BMAN_ADDR \