powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options

[platform/kernel/u-boot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index c045a24..74c2959 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -124,10 +124,10 @@ typedef struct ccsr_i2c {
        u8      res[4096 - 1 * sizeof(struct fsl_i2c_base)];
 } ccsr_i2c_t;
 
-#if defined(CONFIG_MPC8540) \
-       || defined(CONFIG_MPC8541) \
-       || defined(CONFIG_MPC8548) \
-       || defined(CONFIG_MPC8555)
+#if defined(CONFIG_MPC8540) || \
+       defined(CONFIG_MPC8541) || \
+       defined(CONFIG_ARCH_MPC8548) || \
+       defined(CONFIG_MPC8555)
 /* DUART Registers */
 typedef struct ccsr_duart {
        u8      res1[1280];
@@ -1579,7 +1579,7 @@ typedef struct cpc_corenet {
 #define CPC_HDBCR0_CDQ_SPEC_DIS        0x08000000
 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS   0x01000000
 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS  0x00400000
-#define CPC_HDBCR0_SPLRU_LEVEL_EN      0x003c0000
+#define CPC_HDBCR0_SPLRU_LEVEL_EN      0x001e0000
 #endif /* CONFIG_SYS_FSL_CPC */
 
 /* Global Utilities Block */
@@ -2129,7 +2129,7 @@ typedef struct ccsr_gur {
                                        & MPC85xx_PORDEVSR2_DDR_SPD_0) \
                                        >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
 #else
-#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
 #define MPC85xx_PORPLLSR_DDR_RATIO     0x00003f00
 #else
 #define MPC85xx_PORPLLSR_DDR_RATIO     0x00003e00
@@ -2172,7 +2172,7 @@ typedef struct ccsr_gur {
 #if defined(CONFIG_P1010)
 #define MPC85xx_PORDEVSR_IO_SEL                0x00600000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  21
-#elif defined(CONFIG_BSC9132)
+#elif defined(CONFIG_ARCH_BSC9132)
 #define MPC85xx_PORDEVSR_IO_SEL                0x00FE0000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  17
 #elif defined(CONFIG_PPC_C29X)
@@ -2296,7 +2296,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_SPI_MASK                0x00600000
 #define MPC85xx_PMUXCR_SPI             0x00000000
 #endif
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131)
 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ      0x40000000
 #define MPC85xx_PMUXCR_TSEC2_USB               0xC0000000
 #define MPC85xx_PMUXCR_TSEC2_1588_PPS          0x10000000
@@ -2340,7 +2340,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen  0x00000002
 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76          0x00000003
 #endif
-#ifdef CONFIG_BSC9132
+#ifdef CONFIG_ARCH_BSC9132
 #define MPC85xx_PMUXCR0_SIM_SEL_MASK   0x0003b000
 #define MPC85xx_PMUXCR0_SIM_SEL                0x00014000
 #endif
@@ -2379,8 +2379,8 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR2_ETSECUSB_MASK  0x001f8000
 #define MPC85xx_PMUXCR2_USB            0x00150000
 #endif
-#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131)
 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD             0X40000000
 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS            0X80000000
 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42             0xC0000000
@@ -2425,7 +2425,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49              0x00000002
 #endif
        u32     pmuxcr3;
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131)
 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM                 0x40000000
 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51          0x80000000
 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B    0x10000000
@@ -2441,7 +2441,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD                  0x00010000
 #define MPC85xx_PMUXCR3_ANT2_GPO89                     0x00030000
 #endif
-#ifdef CONFIG_BSC9132
+#ifdef CONFIG_ARCH_BSC9132
 #define MPC85xx_PMUXCR3_USB_SEL_MASK   0x0000ff00
 #define MPC85xx_PMUXCR3_UART2_SEL      0x00005000
 #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
@@ -2504,7 +2504,7 @@ typedef struct ccsr_gur {
        u32     ddrdllcr;       /* DDR DLL control */
        u8      res14[12];
        u32     lbcdllcr;       /* LBC DLL control */
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131)
        u8      res15[12];
        u32     halt_req_mask;
 #define HALTED_TO_HALT_REQ_MASK_0      0x80000000
@@ -2953,6 +2953,8 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET          0x21000
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET         0x22000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET         0x23000
+#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET     0xE5000
+#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET     0xE5100
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET                        0xB0000
 #elif defined(CONFIG_TSECV2_1)
@@ -2986,7 +2988,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET         0xE0000
 #define CONFIG_SYS_FSL_SRIO_OFFSET             0xC0000
 
-#if defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9132)
 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET     0x10000
 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
        (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)