p4080/serdes: Implement the XAUI workaround for SERDES9 erratum

[platform/kernel/u-boot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7beb6a7..286ecb9 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1920,9 +1920,57 @@ typedef struct ccsr_gur {
        u32     gpindr;         /* General-purpose input data */
        u8      res5[12];
        u32     pmuxcr;         /* Alt. function signal multiplex control */
+#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
+#define MPC85xx_PMUXCR_TSEC1_0_1588            0x40000000
+#define MPC85xx_PMUXCR_TSEC1_0_RES             0xC0000000
+#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG       0x10000000
+#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12         0x20000000
+#define MPC85xx_PMUXCR_TSEC1_1_RES             0x30000000
+#define MPC85xx_PMUXCR_TSEC1_2_DMA             0x04000000
+#define MPC85xx_PMUXCR_TSEC1_2_GPIO            0x08000000
+#define MPC85xx_PMUXCR_TSEC1_2_RES             0x0C000000
+#define MPC85xx_PMUXCR_TSEC1_3_RES             0x01000000
+#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15         0x02000000
+#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC         0x00400000
+#define MPC85xx_PMUXCR_IFC_ADDR16_USB          0x00800000
+#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2      0x00C00000
+#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC      0x00100000
+#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB       0x00200000
+#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA       0x00300000
+#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA    0x00040000
+#define MPC85xx_PMUXCR_IFC_ADDR19_USB          0x00080000
+#define MPC85xx_PMUXCR_IFC_ADDR19_DMA          0x000C0000
+#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
+#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB       0x00020000
+#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES       0x00030000
+#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC         0x00004000
+#define MPC85xx_PMUXCR_IFC_ADDR22_USB          0x00008000
+#define MPC85xx_PMUXCR_IFC_ADDR22_RES          0x0000C000
+#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC         0x00001000
+#define MPC85xx_PMUXCR_IFC_ADDR23_USB          0x00002000
+#define MPC85xx_PMUXCR_IFC_ADDR23_RES          0x00003000
+#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC         0x00000400
+#define MPC85xx_PMUXCR_IFC_ADDR24_USB          0x00000800
+#define MPC85xx_PMUXCR_IFC_ADDR24_RES          0x00000C00
+#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES                0x00000300
+#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB                0x00000200
+#define MPC85xx_PMUXCR_LCLK_RES                        0x00000040
+#define MPC85xx_PMUXCR_LCLK_USB                        0x00000080
+#define MPC85xx_PMUXCR_LCLK_IFC_CS3            0x000000C0
+#define MPC85xx_PMUXCR_SPI_RES                 0x00000030
+#define MPC85xx_PMUXCR_SPI_GPIO                        0x00000020
+#define MPC85xx_PMUXCR_CAN1_UART               0x00000004
+#define MPC85xx_PMUXCR_CAN1_TDM                        0x00000008
+#define MPC85xx_PMUXCR_CAN1_RES                        0x0000000C
+#define MPC85xx_PMUXCR_CAN2_UART               0x00000001
+#define MPC85xx_PMUXCR_CAN2_TDM                        0x00000002
+#define MPC85xx_PMUXCR_CAN2_RES                        0x00000003
+#endif
 #define MPC85xx_PMUXCR_SD_DATA         0x80000000
 #define MPC85xx_PMUXCR_SDHC_CD         0x40000000
 #define MPC85xx_PMUXCR_SDHC_WP         0x20000000
+#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON        0x01000000
+#define MPC85xx_PMUXCR_TDM_ENA         0x00800000
 #define MPC85xx_PMUXCR_QE0             0x00008000
 #define MPC85xx_PMUXCR_QE1             0x00004000
 #define MPC85xx_PMUXCR_QE2             0x00002000
@@ -1936,7 +1984,42 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_QE10            0x00000020
 #define MPC85xx_PMUXCR_QE11            0x00000010
 #define MPC85xx_PMUXCR_QE12            0x00000008
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PMUXCR_TDM_MASK                0x0001cc00
+#define MPC85xx_PMUXCR_TDM             0x00014800
+#define MPC85xx_PMUXCR_SPI_MASK                0x00600000
+#define MPC85xx_PMUXCR_SPI             0x00000000
+#endif
        u32     pmuxcr2;        /* Alt. function signal multiplex control 2 */
+#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
+#define MPC85xx_PMUXCR2_UART_GPIO              0x40000000
+#define MPC85xx_PMUXCR2_UART_TDM               0x80000000
+#define MPC85xx_PMUXCR2_UART_RES               0xC0000000
+#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN           0x10000000
+#define MPC85xx_PMUXCR2_IRQ2_RES               0x30000000
+#define MPC85xx_PMUXCR2_IRQ3_SRESET            0x04000000
+#define MPC85xx_PMUXCR2_IRQ3_RES               0x0C000000
+#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS         0x01000000
+#define MPC85xx_PMUXCR2_GPIO01_RES             0x03000000
+#define MPC85xx_PMUXCR2_GPIO23_CKSTP           0x00400000
+#define MPC85xx_PMUXCR2_GPIO23_RES             0x00800000
+#define MPC85xx_PMUXCR2_GPIO23_USB             0x00C00000
+#define MPC85xx_PMUXCR2_GPIO4_MCP              0x00100000
+#define MPC85xx_PMUXCR2_GPIO4_RES              0x00200000
+#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT          0x00300000
+#define MPC85xx_PMUXCR2_GPIO5_UDE              0x00040000
+#define MPC85xx_PMUXCR2_GPIO5_RES              0x00080000
+#define MPC85xx_PMUXCR2_READY_ASLEEP           0x00020000
+#define MPC85xx_PMUXCR2_DDR_ECC_MUX            0x00010000
+#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE      0x00008000
+#define MPC85xx_PMUXCR2_POST_EXPOSE            0x00004000
+#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY   0x00002000
+#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE                0x00001000
+#endif
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PMUXCR2_ETSECUSB_MASK  0x001f1000
+#define MPC85xx_PMUXCR2_USB            0x00150000
+#endif
        u8      res6[8];
        u32     devdisr;        /* Device disable control */
 #define MPC85xx_DEVDISR_PCI1           0x80000000
@@ -1998,10 +2081,14 @@ typedef struct ccsr_gur {
        u32     ddrioovcr;      /* DDR IO Override Control */
        u32     tsec12ioovcr;   /* eTSEC 1/2 IO override control */
        u32     tsec34ioovcr;   /* eTSEC 3/4 IO override control */
-       u8      res16[61648];
+       u8      res16[52];
+       u32     sdhcdcr;        /* SDHC debug control register */
+       u8      res17[61592];
 } ccsr_gur_t;
 #endif
 
+#define SDHCDCR_CD_INV         0x80000000 /* invert SDHC card detect */
+
 typedef struct serdes_corenet {
        struct {
                u32     rstctl; /* Reset Control Register */
@@ -2050,6 +2137,8 @@ typedef struct serdes_corenet {
 #define SRDS_TECR0_TEQ_TYPE_2LVL       0x10000000
                u32     res3;
                u32     ttlcr0; /* Transition Tracking Loop Ctrl 0 */
+#define SRDS_TTLCR0_FLT_SEL_MASK       0x3f000000
+#define SRDS_TTLCR0_PM_DIS             0x00004000
                u32     res4[7];
        } lane[24];
        u32 res6[384];