+/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * Copyright 2007,2009-2012 Freescale Semiconductor, Inc.
*/
#ifndef __FSL_PCI_H_
#define PEX_IP_BLK_REV_2_2 0x02080202
#define PEX_IP_BLK_REV_2_3 0x02080203
+#define PEX_IP_BLK_REV_3_0 0x02080300
+
+/* Freescale-specific PCI config registers */
+#define FSL_PCI_PBFR 0x44
+
+#define FSL_PCIE_CFG_RDY 0x4b0
+#define FSL_PCIE_V3_CFG_RDY 0x1
+#define FSL_PROG_IF_AGENT 0x1
+
+#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
+#define PCI_LTSSM_L0 0x16 /* L0 state */
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
int fsl_is_pci_agent(struct pci_controller *hose);
void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
/*
- * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
+ * Common PCI/PCIE Register structure for mpc85xx
*/
/*
u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */
u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
u32 pm_command; /* 0x02c - PCIE PM Command register */
- char res4[3016]; /* (- #xbf8 #x30)3016 */
+ char res3[2188]; /* (0x8bc - 0x30 = 2188) */
+ u32 dbi_ro_wr_en; /* 0x8bc - DBI read only write enable reg */
+ char res4[824]; /* (0xbf8 - 0x8c0 = 824) */
u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
char res23[200];
u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
- char res24[252];
+ char res24[16];
+ u32 pex_csr0; /* 0xf14 - PEX Control/Status register 0*/
+ u32 pex_csr1; /* 0xf18 - PEX Control/Status register 1*/
+ char res25[228];
} ccsr_fsl_pci_t;
#define PCIE_CONFIG_PC 0x00020000
#define PCIE_CONFIG_OB_CK 0x00002000
#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
-#if defined(CONFIG_FSL_CORENET)
-#define FSL_PCIE_COMPAT "fsl,p4080-pcie"
+#if !defined(CONFIG_PCI)
+#define FT_FSL_PCI_SETUP
+#elif defined(CONFIG_FSL_CORENET)
+#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
#define FT_FSL_PCI_SETUP \
FT_FSL_PCIE1_SETUP; \
FT_FSL_PCIE2_SETUP; \
#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
#elif defined(CONFIG_MPC85xx)
#define FSL_PCI_COMPAT "fsl,mpc8540-pci"
+#ifdef CONFIG_SYS_FSL_PCIE_COMPAT
+#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
+#else
#define FSL_PCIE_COMPAT "fsl,mpc8548-pcie"
+#endif
#define FT_FSL_PCI_SETUP \
FT_FSL_PCI1_SETUP; \
FT_FSL_PCI2_SETUP; \