+/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2004-2008,2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
*/
#ifndef __ASM_PPC_FSL_LBC_H
#include <config.h>
#include <common.h>
+#ifdef CONFIG_MPC85xx
+void lbc_sdram_init(void);
+#endif
+
/* BR - Base Registers
*/
#define BR0 0x5000 /* Register offset to immr */
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
+#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360)
#define BR_MS_FCM 0x00000020 /* FCM */
-#ifdef CONFIG_MPC83xx
+#endif
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360)
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#elif defined(CONFIG_MPC85xx)
#define BR_MS_SDRAM 0x00000000 /* SDRAM */
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
-#if !defined(CONFIG_MPC834x)
+#if !defined(CONFIG_ARCH_MPC834X)
#define BR_ATOM 0x0000000C
#define BR_ATOM_SHIFT 2
#endif
#define UPMB 1
#define UPMC 2
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
#else
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
/* Convert an address into the right format for the BR registers */
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
-#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
- ((x & 0x300000000ULL) >> 19)))
+#define BR_PHYS_ADDR(x) \
+ ((u32)(((x) & 0x0ffff8000ULL) | (((x) & 0x300000000ULL) >> 19)))
#else
-#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#define BR_PHYS_ADDR(x) ((u32)(x) & 0xffff8000)
#endif
/* OR - Option Registers
#define OR_GPCM_EHTR_SHIFT 1
#define OR_GPCM_EHTR_CLEAR 0x00000000
#define OR_GPCM_EHTR_SET 0x00000002
+#if !defined(CONFIG_ARCH_MPC8308)
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
+#endif
/* helpers to convert values into an OR address mask (GPCM mode) */
#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
#define OR_SDRAM_XAM_SHIFT 13
#define OR_SDRAM_COLS 0x00001C00
#define OR_SDRAM_COLS_SHIFT 10
+#define OR_SDRAM_MIN_COLS 7
#define OR_SDRAM_ROWS 0x000001C0
#define OR_SDRAM_ROWS_SHIFT 6
+#define OR_SDRAM_MIN_ROWS 9
#define OR_SDRAM_PMSEL 0x00000020
#define OR_SDRAM_PMSEL_SHIFT 5
#define OR_SDRAM_EAD 0x00000001
#define LBCR_EPAR_SHIFT 16
#define LBCR_BMT 0x0000FF00
#define LBCR_BMT_SHIFT 8
+#define LBCR_BMTPS 0x0000000F
+#define LBCR_BMTPS_SHIFT 0
/* LCRR - Clock Ratio Register
*/
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
-#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
- defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
- defined(CONFIG_MPC8560)
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
+ defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
#define LSDMR_BSMA1516 (3 << (31 - 10))
#define LSDMR_BSMA1617 (4 << (31 - 10))
#define LSDMR_RFCR5 (3 << (31 - 16))
+#define LSDMR_RFCR8 (5 << (31 - 16))
#define LSDMR_RFCR16 (7 << (31 - 16))
#define LSDMR_PRETOACT3 (3 << (31 - 19))
+#define LSDMR_PRETOACT6 (5 << (31 - 19))
#define LSDMR_PRETOACT7 (7 << (31 - 19))
#define LSDMR_ACTTORW3 (3 << (31 - 22))
#define LSDMR_ACTTORW7 (7 << (31 - 22))
#define LSDMR_ACTTORW6 (6 << (31 - 22))
#define LSDMR_BL8 (1 << (31 - 23))
#define LSDMR_WRC2 (2 << (31 - 27))
+#define LSDMR_WRC3 (3 << (31 - 27))
#define LSDMR_WRC4 (0 << (31 - 27))
#define LSDMR_BUFCMD (1 << (31 - 29))
#define LSDMR_CL3 (3 << (31 - 31))
extern void upmconfig(uint upm, uint *table, uint size);
#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
+#define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr))
+#define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr))
#define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
#define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
#define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))