+/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
*/
#ifndef __ASM_PPC_FSL_LBC_H
#define __ASM_PPC_FSL_LBC_H
#include <config.h>
+#include <common.h>
+
+#ifdef CONFIG_MPC85xx
+void lbc_sdram_init(void);
+#endif
/* BR - Base Registers
*/
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
+#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360)
#define BR_MS_FCM 0x00000020 /* FCM */
-#ifdef CONFIG_MPC83xx
+#endif
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360)
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#elif defined(CONFIG_MPC85xx)
#define BR_MS_SDRAM 0x00000000 /* SDRAM */
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
-#if !defined(CONFIG_MPC834x)
+#if !defined(CONFIG_ARCH_MPC834X)
#define BR_ATOM 0x0000000C
#define BR_ATOM_SHIFT 2
#endif
#define BR_V 0x00000001
#define BR_V_SHIFT 0
+#define BR_UPMx_TO_MSEL(x) ((x + 4) << BR_MSEL_SHIFT)
+
#define UPMA 0
#define UPMB 1
#define UPMC 2
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
#else
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
/* Convert an address into the right format for the BR registers */
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
-#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
- ((x & 0x300000000ULL) >> 19)))
+#define BR_PHYS_ADDR(x) \
+ ((u32)(((x) & 0x0ffff8000ULL) | (((x) & 0x300000000ULL) >> 19)))
#else
-#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#define BR_PHYS_ADDR(x) ((u32)(x) & 0xffff8000)
#endif
/* OR - Option Registers
#define OR_GPCM_SETA_SHIFT 3
#define OR_GPCM_TRLX 0x00000004
#define OR_GPCM_TRLX_SHIFT 2
+#define OR_GPCM_TRLX_CLEAR 0x00000000
+#define OR_GPCM_TRLX_SET 0x00000004
#define OR_GPCM_EHTR 0x00000002
#define OR_GPCM_EHTR_SHIFT 1
+#define OR_GPCM_EHTR_CLEAR 0x00000000
+#define OR_GPCM_EHTR_SET 0x00000002
+#if !defined(CONFIG_ARCH_MPC8308)
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
+#endif
/* helpers to convert values into an OR address mask (GPCM mode) */
#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
#define OR_SDRAM_XAM_SHIFT 13
#define OR_SDRAM_COLS 0x00001C00
#define OR_SDRAM_COLS_SHIFT 10
+#define OR_SDRAM_MIN_COLS 7
#define OR_SDRAM_ROWS 0x000001C0
#define OR_SDRAM_ROWS_SHIFT 6
+#define OR_SDRAM_MIN_ROWS 9
#define OR_SDRAM_PMSEL 0x00000020
#define OR_SDRAM_PMSEL_SHIFT 5
#define OR_SDRAM_EAD 0x00000001
#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
+#define MxMR_UWPL 0x08000000 /* LUPWAIT Polarity Mask */
#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
#define MxMR_OP_WARR 0x10000000 /* Write to Array */
#define MxMR_OP_RARR 0x20000000 /* Read from Array */
#define LBCR_EPAR_SHIFT 16
#define LBCR_BMT 0x0000FF00
#define LBCR_BMT_SHIFT 8
+#define LBCR_BMTPS 0x0000000F
+#define LBCR_BMTPS_SHIFT 0
/* LCRR - Clock Ratio Register
*/
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
-#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
- defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
- defined(CONFIG_MPC8560)
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
+ defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
#define LSDMR_BSMA1516 (3 << (31 - 10))
#define LSDMR_BSMA1617 (4 << (31 - 10))
#define LSDMR_RFCR5 (3 << (31 - 16))
+#define LSDMR_RFCR8 (5 << (31 - 16))
#define LSDMR_RFCR16 (7 << (31 - 16))
#define LSDMR_PRETOACT3 (3 << (31 - 19))
+#define LSDMR_PRETOACT6 (5 << (31 - 19))
#define LSDMR_PRETOACT7 (7 << (31 - 19))
#define LSDMR_ACTTORW3 (3 << (31 - 22))
#define LSDMR_ACTTORW7 (7 << (31 - 22))
#define LSDMR_ACTTORW6 (6 << (31 - 22))
#define LSDMR_BL8 (1 << (31 - 23))
#define LSDMR_WRC2 (2 << (31 - 27))
+#define LSDMR_WRC3 (3 << (31 - 27))
#define LSDMR_WRC4 (0 << (31 - 27))
#define LSDMR_BUFCMD (1 << (31 - 29))
#define LSDMR_CL3 (3 << (31 - 31))
#define LTESR_CC 0x00000001
#ifndef __ASSEMBLY__
-/*
- * Local Bus Controller Registers.
- */
-typedef struct lbus_bank {
- u32 br; /* Base Register */
- u32 or; /* Option Register */
-} lbus_bank_t;
-
-typedef struct fsl_lbus {
- lbus_bank_t bank[8];
- u8 res0[0x28];
- u32 mar; /* UPM Address Register */
- u8 res1[0x4];
- u32 mamr; /* UPMA Mode Register */
- u32 mbmr; /* UPMB Mode Register */
- u32 mcmr; /* UPMC Mode Register */
- u8 res2[0x8];
- u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
- u32 mdr; /* UPM Data Register */
- u8 res3[0x4];
- u32 lsor; /* Special Operation Initiation Register */
- u32 lsdmr; /* SDRAM Mode Register */
- u8 res4[0x8];
- u32 lurt; /* UPM Refresh Timer */
- u32 lsrt; /* SDRAM Refresh Timer */
- u8 res5[0x8];
- u32 ltesr; /* Transfer Error Status Register */
- u32 ltedr; /* Transfer Error Disable Register */
- u32 lteir; /* Transfer Error Interrupt Register */
- u32 lteatr; /* Transfer Error Attributes Register */
- u32 ltear; /* Transfer Error Address Register */
- u8 res6[0xC];
- u32 lbcr; /* Configuration Register */
- u32 lcrr; /* Clock Ratio Register */
- u8 res7[0x8];
- u32 fmr; /* Flash Mode Register */
- u32 fir; /* Flash Instruction Register */
- u32 fcr; /* Flash Command Register */
- u32 fbar; /* Flash Block Addr Register */
- u32 fpar; /* Flash Page Addr Register */
- u32 fbcr; /* Flash Byte Count Register */
- u8 res8[0xF08];
-} fsl_lbus_t;
-#endif /* __ASSEMBLY__ */
+#include <asm/io.h>
+
+extern void print_lbc_regs(void);
+extern void init_early_memctl_regs(void);
+extern void upmconfig(uint upm, uint *table, uint size);
+#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
+#define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr))
+#define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr))
+#define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
+#define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
+#define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
+#define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
+
+typedef struct lbc_bank {
+ u32 br;
+ u32 or;
+} lbc_bank_t;
+
+/* Local Bus Controller Registers */
+typedef struct fsl_lbc {
+ lbc_bank_t bank[8];
+ u8 res1[40];
+ u32 mar; /* LBC UPM Addr */
+ u8 res2[4];
+ u32 mamr; /* LBC UPMA Mode */
+ u32 mbmr; /* LBC UPMB Mode */
+ u32 mcmr; /* LBC UPMC Mode */
+ u8 res3[8];
+ u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */
+ u32 mdr; /* LBC UPM Data */
+#ifdef CONFIG_FSL_ELBC
+ u8 res4[4];
+ u32 lsor;
+ u8 res5[12];
+ u32 lurt; /* LBC UPM Refresh Timer */
+ u8 res6[4];
+#else
+ u8 res4[8];
+ u32 lsdmr; /* LBC SDRAM Mode */
+ u8 res5[8];
+ u32 lurt; /* LBC UPM Refresh Timer */
+ u32 lsrt; /* LBC SDRAM Refresh Timer */
+#endif
+ u8 res7[8];
+ u32 ltesr; /* LBC Transfer Error Status */
+ u32 ltedr; /* LBC Transfer Error Disable */
+ u32 lteir; /* LBC Transfer Error IRQ */
+ u32 lteatr; /* LBC Transfer Error Attrs */
+ u32 ltear; /* LBC Transfer Error Addr */
+ u8 res8[12];
+ u32 lbcr; /* LBC Configuration */
+ u32 lcrr; /* LBC Clock Ratio */
+#ifdef CONFIG_NAND_FSL_ELBC
+ u8 res9[0x8];
+ u32 fmr; /* Flash Mode Register */
+ u32 fir; /* Flash Instruction Register */
+ u32 fcr; /* Flash Command Register */
+ u32 fbar; /* Flash Block Addr Register */
+ u32 fpar; /* Flash Page Addr Register */
+ u32 fbcr; /* Flash Byte Count Register */
+ u8 res10[0xF08];
+#else
+ u8 res9[0xF28];
+#endif
+} fsl_lbc_t;
+
+#endif /* __ASSEMBLY__ */
#endif /* __ASM_PPC_FSL_LBC_H */
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