Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / arch / powerpc / include / asm / config_mpc85xx.h

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 946e74a..f25ba1a 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -116,7 +116,9 @@
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
 #define CONFIG_SYS_NUM_FM1_10GEC       1
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
+#endif
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       32
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
@@ -331,9 +333,6 @@
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_FM_PLAT_CLK_DIV 1
 #define CONFIG_SYS_FM1_CLK             CONFIG_FM_PLAT_CLK_DIV
-#define CONFIG_SYS_SDHC_CLK            0/* Select SDHC CLK begining from PLL1
-                                           per rcw field value */
-#define CONFIG_SYS_SDHC_CLK_2_PLL      /* Select SDHC CLK from 2 PLLs */
 #define CONFIG_SYS_FM_MURAM_SIZE       0x30000
 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
@@ -362,8 +361,6 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_FM1_CLK             0
-#define CONFIG_SYS_SDHC_CLK            0/* Select SDHC CLK begining from PLL1
-                                           per rcw field value */
 #define CONFIG_QBMAN_CLK_DIV           1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x30000
 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
@@ -402,9 +399,6 @@
 #define CONFIG_PME_PLAT_CLK_DIV                1
 #define CONFIG_SYS_PME_CLK             CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FM1_CLK             0
-#define CONFIG_SYS_SDHC_CLK            1/* Select SDHC CLK begining from PLL2
-                                           per rcw field value */
-#define CONFIG_SYS_SDHC_CLK_2_PLL      /* Select SDHC CLK from 2 PLLs */
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000