#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#elif defined(CONFIG_ARCH_MPC8569)
-#define QE_MURAM_SIZE 0x20000UL
-#define MAX_QE_RISC 4
-#define QE_NUM_OF_SNUM 46
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_RMU
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
#define QE_NUM_OF_SNUM 28
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#elif defined(CONFIG_ARCH_P1022)
-#define CONFIG_TSECV2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-
#elif defined(CONFIG_ARCH_P1023)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
-#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
-#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_NUM_FMAN 1
-#define CONFIG_SYS_NUM_FM1_DTSEC 5
-#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV 32
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
-
#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FMAN_V3
#define CONFIG_FM_PLAT_CLK_DIV 1
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
-#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
- per rcw field value */
-#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 0
-#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
- per rcw field value */
#define CONFIG_QBMAN_CLK_DIV 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#elif defined(CONFIG_ARCH_T2080)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#elif defined(CONFIG_ARCH_T2081)
-#define CONFIG_SYS_NUM_FM1_DTSEC 6
-#define CONFIG_SYS_NUM_FM1_10GEC 2
#endif
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FM1_CLK 0
-#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
- per rcw field value */
-#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000