atmel_lcd: Allow contrast polarity to be either positive or negative

[platform/kernel/u-boot.git] / arch / powerpc / cpu / ppc4xx / cpu_init.c

diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 8a6e545..d54b30e 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -23,10 +23,10 @@
 
 #include <common.h>
 #include <watchdog.h>
-#include <ppc4xx_enet.h>
+#include <asm/ppc4xx-emac.h>
 #include <asm/processor.h>
-#include <asm/gpio.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/ppc4xx.h>
 
 #if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
 DECLARE_GLOBAL_DATA_PTR;
@@ -36,6 +36,26 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CONFIG_SYS_PLL_RECONFIG        0
 #endif
 
+#if defined(CONFIG_440EPX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+static void reset_with_rli(void)
+{
+       u32 reg;
+
+       /*
+        * Set reload inhibit so configuration will persist across
+        * processor resets
+        */
+       mfcpr(CPR0_ICFG, reg);
+       reg |= CPR0_ICFG_RLI_MASK;
+       mtcpr(CPR0_ICFG, reg);
+
+       /* Reset processor if configuration changed */
+       __asm__ __volatile__ ("sync; isync");
+       mtspr(SPRN_DBCR0, 0x20000000);
+}
+#endif
+
 void reconfigure_pll(u32 new_cpu_freq)
 {
 #if defined(CONFIG_440EPX)
@@ -122,22 +142,28 @@ void reconfigure_pll(u32 new_cpu_freq)
         * modify it.
         */
        if (temp == 1) {
-               mfcpr(CPR0_PLLD, reg);
-               /* Get current value of fbdv.  */
-               temp = (reg & PLLD_FBDV_MASK) >> 24;
-               fbdv = temp ? temp : 32;
-               /* Get current value of lfbdv. */
-               temp = (reg & PLLD_LFBDV_MASK);
-               lfbdv = temp ? temp : 64;
                /*
                 * Load register that contains current boot strapping option.
                 */
                mfcpr(CPR0_ICFG, reg);
-               /* Shift strapping option into low 3 bits.*/
-               reg = (reg >> 28);
+               /*
+                * Strapping option bits (ICS) are already in correct position,
+                * only masking needed.
+                */
+               reg &= CPR0_ICFG_ICS_MASK;
 
                if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
                    (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
+                       mfcpr(CPR0_PLLD, reg);
+
+                       /* Get current value of fbdv.  */
+                       temp = (reg & PLLD_FBDV_MASK) >> 24;
+                       fbdv = temp ? temp : 32;
+
+                       /* Get current value of lfbdv. */
+                       temp = (reg & PLLD_LFBDV_MASK);
+                       lfbdv = temp ? temp : 64;
+
                        /*
                         * Get current value of FWDVA. Assign current FWDVA to
                         * new FWDVB.
@@ -145,12 +171,14 @@ void reconfigure_pll(u32 new_cpu_freq)
                        mfcpr(CPR0_PLLD, reg);
                        target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
                        fwdvb = target_fwdvb ? target_fwdvb : 8;
+
                        /*
                         * Get current value of FWDVB. Assign current FWDVB to
                         * new FWDVA.
                         */
                        target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
                        fwdva = target_fwdva ? target_fwdva : 16;
+
                        /*
                         * Update CPR0_PLLD with switched FWDVA and FWDVB.
                         */
@@ -161,24 +189,34 @@ void reconfigure_pll(u32 new_cpu_freq)
                                ((fbdv == 32 ? 0 : fbdv) << 24) |
                                (lfbdv == 64 ? 0 : lfbdv);
                        mtcpr(CPR0_PLLD, reg);
+
                        /* Acknowledge that a reset is required. */
                        reset_needed = 1;
                }
        }
 
-       if (reset_needed) {
+       /* Now reset the CPU if needed */
+       if (reset_needed)
+               reset_with_rli();
+#endif
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+       u32 reg;
+
+       /*
+        * See "9.2.1.1 Booting with Option E" in the 460EX/GT
+        * users manual
+        */
+       mfcpr(CPR0_PLLC, reg);
+       if ((reg & (CPR0_PLLC_RST | CPR0_PLLC_ENG)) == CPR0_PLLC_RST) {
                /*
-                * Set reload inhibit so configuration will persist across
-                * processor resets
+                * Set engage bit
                 */
-               mfcpr(CPR0_ICFG, reg);
-               reg &= ~CPR0_ICFG_RLI_MASK;
-               reg |= 1 << 31;
-               mtcpr(CPR0_ICFG, reg);
+               reg = (reg & ~CPR0_PLLC_RST) | CPR0_PLLC_ENG;
+               mtcpr(CPR0_PLLC, reg);
 
-               /* Reset processor if configuration changed */
-               __asm__ __volatile__ ("sync; isync");
-               mtspr(SPRN_DBCR0, 0x20000000);
+               /* Now reset the CPU */
+               reset_with_rli();
        }
 #endif
 }
@@ -228,7 +266,7 @@ cpu_init_f (void)
        /*
         * Set EMAC noise filter bits
         */
-       mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
+       mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE);
 #endif /* CONFIG_405EP */
 
 #if defined(CONFIG_SYS_4xx_GPIO_TABLE)
@@ -359,10 +397,10 @@ cpu_init_f (void)
        /*
         * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
         */
-       mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) |
-             PLB0_ACR_RDP_4DEEP);
-       mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) |
-             PLB1_ACR_RDP_4DEEP);
+       mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
+             PLB4Ax_ACR_RDP_4DEEP);
+       mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
+             PLB4Ax_ACR_RDP_4DEEP);
 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
 }