ppc4xx: Big header cleanup, mostly PPC440 related

[platform/kernel/u-boot.git] / arch / powerpc / cpu / ppc4xx / cpu_init.c

diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index c04eede..677a4b5 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -23,10 +23,10 @@
 
 #include <common.h>
 #include <watchdog.h>
-#include <ppc4xx_enet.h>
+#include <asm/ppc4xx-emac.h>
 #include <asm/processor.h>
-#include <asm/gpio.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/ppc4xx.h>
 
 #if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
 DECLARE_GLOBAL_DATA_PTR;
@@ -142,22 +142,28 @@ void reconfigure_pll(u32 new_cpu_freq)
         * modify it.
         */
        if (temp == 1) {
-               mfcpr(CPR0_PLLD, reg);
-               /* Get current value of fbdv.  */
-               temp = (reg & PLLD_FBDV_MASK) >> 24;
-               fbdv = temp ? temp : 32;
-               /* Get current value of lfbdv. */
-               temp = (reg & PLLD_LFBDV_MASK);
-               lfbdv = temp ? temp : 64;
                /*
                 * Load register that contains current boot strapping option.
                 */
                mfcpr(CPR0_ICFG, reg);
-               /* Shift strapping option into low 3 bits.*/
-               reg = (reg >> 28);
+               /*
+                * Strapping option bits (ICS) are already in correct position,
+                * only masking needed.
+                */
+               reg &= CPR0_ICFG_ICS_MASK;
 
                if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
                    (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
+                       mfcpr(CPR0_PLLD, reg);
+
+                       /* Get current value of fbdv.  */
+                       temp = (reg & PLLD_FBDV_MASK) >> 24;
+                       fbdv = temp ? temp : 32;
+
+                       /* Get current value of lfbdv. */
+                       temp = (reg & PLLD_LFBDV_MASK);
+                       lfbdv = temp ? temp : 64;
+
                        /*
                         * Get current value of FWDVA. Assign current FWDVA to
                         * new FWDVB.
@@ -165,12 +171,14 @@ void reconfigure_pll(u32 new_cpu_freq)
                        mfcpr(CPR0_PLLD, reg);
                        target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
                        fwdvb = target_fwdvb ? target_fwdvb : 8;
+
                        /*
                         * Get current value of FWDVB. Assign current FWDVB to
                         * new FWDVA.
                         */
                        target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
                        fwdva = target_fwdva ? target_fwdva : 16;
+
                        /*
                         * Update CPR0_PLLD with switched FWDVA and FWDVB.
                         */
@@ -181,6 +189,7 @@ void reconfigure_pll(u32 new_cpu_freq)
                                ((fbdv == 32 ? 0 : fbdv) << 24) |
                                (lfbdv == 64 ? 0 : lfbdv);
                        mtcpr(CPR0_PLLD, reg);
+
                        /* Acknowledge that a reset is required. */
                        reset_needed = 1;
                }
@@ -388,10 +397,10 @@ cpu_init_f (void)
        /*
         * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
         */
-       mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) |
-             PLB0_ACR_RDP_4DEEP);
-       mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) |
-             PLB1_ACR_RDP_4DEEP);
+       mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
+             PLB4Ax_ACR_RDP_4DEEP);
+       mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
+             PLB4Ax_ACR_RDP_4DEEP);
 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
 }