Merge branch 'master' of /home/wd/git/u-boot/master

[platform/kernel/u-boot.git] / arch / powerpc / cpu / ppc4xx / 4xx_ibm_ddr2_autocalib.c

diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index aed0ed7..2cfc37f 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -83,11 +83,6 @@ struct ddrautocal {
        u32 flags;
 };
 
-struct sdram_timing {
-       u32 wrdtr;
-       u32 clktr;
-};
-
 struct sdram_timing_clks {
        u32 wrdtr;
        u32 clktr;
@@ -145,11 +140,12 @@ void
 spd_ddr_init_hang(void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 #endif /* defined(CONFIG_SPD_EEPROM) */
 
-ulong __ddr_scan_option(ulong default_val)
+struct sdram_timing *__ddr_scan_option(struct sdram_timing *default_val)
 {
        return default_val;
 }
-ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option")));
+struct sdram_timing *ddr_scan_option(struct sdram_timing *)
+       __attribute__((weak, alias("__ddr_scan_option")));
 
 u32 __ddr_rdss_opt(u32 default_val)
 {
@@ -771,6 +767,13 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
 
        debug("\n\n");
 
+#if defined(CONFIG_DDR_RFDC_FIXED)
+       mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
+       size = 512;
+       rffd_average = CONFIG_DDR_RFDC_FIXED & SDRAM_RFDC_RFFD_MASK;
+       mfsdram(SDRAM_RDCC, rdcc);      /* record this value */
+       cal->rdcc = rdcc;
+#else /* CONFIG_DDR_RFDC_FIXED */
        in_window = 0;
        rdcc = 0;
 
@@ -834,6 +837,7 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
                rffd_average = SDRAM_RFDC_RFFD_MAX;
 
        mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
+#endif /* CONFIG_DDR_RFDC_FIXED */
 
        rffd = rffd_average;
        in_window = 0;
@@ -931,7 +935,7 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
  * known working {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]} value
  * pairs via a board defined ddr_scan_option() function.
  */
-struct sdram_timing full_scan_options[] = {
+static struct sdram_timing full_scan_options[] = {
        {0, 0}, {0, 1}, {0, 2}, {0, 3},
        {1, 0}, {1, 1}, {1, 2}, {1, 3},
        {2, 0}, {2, 1}, {2, 2}, {2, 3},
@@ -970,10 +974,7 @@ u32 DQS_autocalibration(void)
 
        memset(&tcal, 0, sizeof(tcal));
 
-       ddr_scan_option((ulong)full_scan_options);
-
-       scan_list =
-             (struct sdram_timing *)ddr_scan_option((ulong)full_scan_options);
+       scan_list = ddr_scan_option(full_scan_options);
 
        mfsdram(SDRAM_MCOPT1, val);
        if ((val & SDRAM_MCOPT1_MCHK_CHK_REP) == SDRAM_MCOPT1_MCHK_CHK_REP)
@@ -984,7 +985,7 @@ u32 DQS_autocalibration(void)
        puts(str);
 
 #if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
-       i = getenv_r("autocalib", tmp, sizeof(tmp));
+       i = getenv_f("autocalib", tmp, sizeof(tmp));
        if (i < 0)
                strcpy(tmp, CONFIG_AUTOCALIB);
 
@@ -1218,10 +1219,14 @@ u32 DQS_autocalibration(void)
                debug("*** best_result: read value SDRAM_RQDC 0x%08x\n",
                                rqdc_reg);
 
+#if defined(CONFIG_DDR_RFDC_FIXED)
+               mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
+#else /* CONFIG_DDR_RFDC_FIXED */
                mfsdram(SDRAM_RFDC, rfdc_reg);
                rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
                mtsdram(SDRAM_RFDC, rfdc_reg |
                                SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd));
+#endif /* CONFIG_DDR_RFDC_FIXED */
 
                mfsdram(SDRAM_RFDC, rfdc_reg);
                debug("*** best_result: read value SDRAM_RFDC 0x%08x\n",