#include "ecc.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
do { \
u32 data; \
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void update_rdcc(void)
{
u32 val;
}
}
}
-#endif
#if defined(CONFIG_440)
/*
#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
-#if !defined(CONFIG_NAND_SPL)
/*-----------------------------------------------------------------------------+
* sdram_memsize
*-----------------------------------------------------------------------------*/
val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
printf(", CL%d)", val);
}
-#endif /* !CONFIG_NAND_SPL */
#if defined(CONFIG_SPD_EEPROM)
}
/*-----------------------------------------------------------------------------+
- * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
+ * dram_init. Initializes the 440SP Memory Queue and DDR SDRAM controller.
* Note: This routine runs from flash with a stack set up in the chip's
* sram space. It is important that the routine does not require .sbss, .bss or
* .data sections. It also cannot call routines that require these sections.
*-----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------
- * Function: initdram
+ * Function: dram_init
* Description: Configures SDRAM memory banks for DDR operation.
* Auto Memory Configuration option reads the DDR SDRAM EEPROMs
* via the IIC bus and then configures the DDR SDRAM memory
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
int write_recovery;
phys_size_t dram_size = 0;
+ if (IS_ENABLED(CONFIG_SYS_RAMBOOT)) {
+ /*
+ * Reduce RAM size to avoid overwriting memory used by
+ * current stack? Not sure what is happening.
+ */
+ gd->ram_size = sdram_memsize() / 2;
+
+ return 0;
+ }
+
num_dimm_banks = sizeof(iic0_dimm_addr);
/*------------------------------------------------------------------
*/
set_mcsr(get_mcsr());
- return sdram_memsize();
+ gd->ram_size = sdram_memsize();
+
+ return 0;
}
static void get_spd_info(unsigned long *dimm_populated,
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE)
- t_wr_ns = max(t_wr_ns,
+ t_wr_ns = max(t_wr_ns, (unsigned long)
spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
}
else
sdram_ddr1 = false;
- t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
- t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
- t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
- t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
- t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
- t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
+ t_rcd_ns = max(t_rcd_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
+ t_rrd_ns = max(t_rrd_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
+ t_rp_ns = max(t_rp_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
+ t_ras_ns = max(t_ras_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 30));
+ t_rc_ns = max(t_rc_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 41));
+ t_rfc_ns = max(t_rfc_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 42));
}
}
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE) {
- t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
- t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
- t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
+ t_wpc_ns = max(t_wtr_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
+ t_wtr_ns = max(t_wtr_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
+ t_rpc_ns = max(t_rpc_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
}
}
for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE)
- ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
+ ecc = max(ecc,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11));
}
if (ecc == 0)
return;
#else /* CONFIG_SPD_EEPROM */
/*-----------------------------------------------------------------------------
- * Function: initdram
+ * Function: dram_init
* Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
* The configuration is performed using static, compile-
* time parameters.
* Configures the PPC405EX(r) and PPC460EX/GT
*---------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
- /*
- * Only run this SDRAM init code once. For NAND booting
- * targets like Kilauea, we call initdram() early from the
- * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
- * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
- * which calls initdram() again. This time the controller
- * mustn't be reconfigured again since we're already running
- * from SDRAM.
- */
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
unsigned long val;
#if defined(CONFIG_440)
#endif
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*------------------------------------------------------------------
| DQS calibration.
+-----------------------------------------------------------------*/
DQS_autocalibration();
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
/*
set_mcsr(get_mcsr());
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
-#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
+ gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
- return (CONFIG_SYS_MBYTES_SDRAM << 20);
+ return 0;
}
#endif /* CONFIG_SPD_EEPROM */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_440)
u32 mfdcr_any(u32 dcr)
{
}
}
#endif /* defined(CONFIG_440) */
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
inline void ppc4xx_ibm_ddr2_register_dump(void)
{