global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc8xxx / srio.c

diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 0ab9aac..c815d19 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -1,15 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <config.h>
+#include <log.h>
+#include <time.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
-#include <asm/errno.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 #define SRIO_PORT_ACCEPT_ALL 0x10000001
@@ -31,12 +33,12 @@
        #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
 #endif
        #define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
-       #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+       #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC85xx)
        #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
        #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
        #define _DEVDISR_RMU   MPC85xx_DEVDISR_RMSG
-       #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+       #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC86xx)
        #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
        #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
@@ -77,9 +79,9 @@ static int srio_erratum_a004034(u8 port)
        int idx, first, last;
        u32 i;
        unsigned long long end_tick;
-       struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+       struct ccsr_rio *srio_regs = (void *)CFG_SYS_FSL_SRIO_ADDR;
 
-       srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+       srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
        conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
                        >> (12 - port * 4)) & 0x3;
        init_lane = (in_be32((void *)&srio_regs->lp_serial
@@ -289,7 +291,7 @@ void srio_init(void)
 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 void srio_boot_master(int port)
 {
-       struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+       struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
 
        /* set port accept-all */
        out_be32((void *)&srio->impl.port[port - 1].ptaacr,
@@ -341,7 +343,7 @@ void srio_boot_master(int port)
 
 void srio_boot_master_release_slave(int port)
 {
-       struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+       struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
        u32 escsr;
        debug("SRIOBOOT - MASTER: "
                        "Check the port status and release slave core ...\n");