global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc8xxx / law.c

diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index a401083..dd27416 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -1,23 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <display_options.h>
+#include <asm/bitops.h>
+#include <asm/global_data.h>
 #include <linux/compiler.h>
 #include <asm/fsl_law.h>
 #include <asm/io.h>
+#include <linux/log2.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
 
 #ifdef CONFIG_FSL_CORENET
-#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
+#define LAW_BASE (CFG_SYS_FSL_CORENET_CCM_ADDR)
 #define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
 #define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
 #define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
@@ -77,7 +80,7 @@ void disable_law(u8 idx)
 }
 
 #if !defined(CONFIG_NAND_SPL) && \
-       (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
+       (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
 static int get_law_entry(u8 i, struct law_entry *e)
 {
        u32 lawar;
@@ -108,7 +111,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 }
 
 #if !defined(CONFIG_NAND_SPL) && \
-       (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
+       (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
 int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 {
        u32 idx;
@@ -187,7 +190,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
        if (start == 0)
                start_align = 1ull << (LAW_SIZE_32G + 1);
        else
-               start_align = 1ull << (ffs64(start) - 1);
+               start_align = 1ull << (__ffs64(start));
        law_sz = min(start_align, sz);
        law_sz_enc = __ilog2_u64(law_sz) - 1;
 
@@ -202,7 +205,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
        if (sz) {
                start += law_sz;
 
-               start_align = 1ull << (ffs64(start) - 1);
+               start_align = 1ull << (__ffs64(start));
                law_sz = min(start_align, sz);
                law_sz_enc = __ilog2_u64(law_sz) - 1;
 
@@ -221,6 +224,32 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
 }
 #endif /* not SPL */
 
+void disable_non_ddr_laws(void)
+{
+       int i;
+       int id;
+       for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
+               u32 lawar = in_be32(LAWAR_ADDR(i));
+
+               if (lawar & LAW_EN) {
+                       id = (lawar & ~LAW_EN) >> 20;
+                       switch (id) {
+                       case LAW_TRGT_IF_DDR_1:
+                       case LAW_TRGT_IF_DDR_2:
+                       case LAW_TRGT_IF_DDR_3:
+                       case LAW_TRGT_IF_DDR_4:
+                       case LAW_TRGT_IF_DDR_INTRLV:
+                       case LAW_TRGT_IF_DDR_INTLV_34:
+                       case LAW_TRGT_IF_DDR_INTLV_123:
+                       case LAW_TRGT_IF_DDR_INTLV_1234:
+                                               continue;
+                       default:
+                                               disable_law(i);
+                       }
+               }
+       }
+}
+
 void init_laws(void)
 {
        int i;
@@ -233,6 +262,23 @@ void init_laws(void)
 #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
 #endif
 
+#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500) && \
+                                               !defined(CONFIG_E500MC)
+       /* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms,
+        * which is not disabled before transferring the control to uboot.
+        * Disable the LAW 0 entry here.
+        */
+       disable_law(0);
+#endif
+
+#if !defined(CONFIG_NXP_ESBC)
+       /*
+        * if any non DDR LAWs has been created earlier, remove them before
+        * LAW table is parsed.
+       */
+       disable_non_ddr_laws();
+#endif
+
        /*
         * Any LAWs that were set up before we booted assume they are meant to
         * be around and mark them used.
@@ -244,15 +290,6 @@ void init_laws(void)
                        gd->arch.used_laws |= (1 << i);
        }
 
-#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \
-       (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
-       /*
-        * in SPL boot we've already parsed the law_table and setup those LAWs
-        * so don't do it again.
-        */
-       return;
-#endif
-
        for (i = 0; i < num_law_entries; i++) {
                if (law_table[i].index == -1)
                        set_next_law(law_table[i].addr, law_table[i].size,
@@ -264,7 +301,7 @@ void init_laws(void)
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
        /* check RCW to get which port is used for boot */
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
        u32 bootloc = in_be32(&gur->rcwsr[6]);
        /*
         * in SRIO or PCIE boot we need to set specail LAWs for
@@ -316,5 +353,5 @@ void init_laws(void)
        }
 #endif
 
-       return ;
+       return;
 }