Coding Style cleanup: remove trailing white space

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / start.S

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 5542d0a..d329aa8 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -2,23 +2,7 @@
  * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
  * Copyright (C) 2003  Motorola,Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
@@ -49,7 +33,8 @@
 #define MINIMAL_SPL
 #endif
 
-#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
+       !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define NOR_BOOT
 #endif
 
@@ -123,6 +108,14 @@ _start_e500:
        isync
 2:
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
+       msync
+       isync
+       mfspr   r3, SPRN_HDBCR0
+       oris    r3, r3, 0x0080
+       mtspr   SPRN_HDBCR0, r3
+#endif
+
 
 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
        /* ISBC uses L2 as stack.
@@ -734,7 +727,8 @@ enable_l2_cluster_l2:
        isync
        and.    r1, r0, r4
        bne     1b
-       lis     r4, L2CSR0_L2E@h
+       lis     r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
+       ori     r4, r4, (L2CSR0_L2REP_MODE)@l
        sync
        stw     r4, 0(r3)       /* enable L2 */
 delete_ccsr_l2_tlb:
@@ -1794,7 +1788,7 @@ clear_bss:
        stw     r0,0(r3)
        addi    r3,r3,4
        cmplw   0,r3,r4
-       bne     5b
+       blt     5b
 6:
 
        mr      r3,r9           /* Init Data pointer            */
@@ -1905,6 +1899,7 @@ unlock_ram_in_cache:
        slwi    r4,r4,(10 - 1 - L1_CACHE_SHIFT)
        mtctr   r4
 1:     dcbi    r0,r3
+       dcblc   r0,r3
        addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
        bdnz    1b
        sync