powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index ce47532..6c2bc34 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -39,6 +39,10 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info (sys_info_t * sysInfo)
 {
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+       struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+       u32 ccr;
+#endif
 #ifdef CONFIG_FSL_CORENET
        volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
        unsigned int cpu;
@@ -81,7 +85,9 @@ void get_sys_info (sys_info_t * sysInfo)
        sysInfo->freqDDRBus = sysclk;
 
        sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-       mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+       mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
+                       FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
+                       & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
        if (mem_pll_rat > 2)
                sysInfo->freqDDRBus *= mem_pll_rat;
        else
@@ -112,6 +118,8 @@ void get_sys_info (sys_info_t * sysInfo)
 #define HWA_ASYNC_DIV  0x04000000
 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
 #define HWA_CC_PLL     1
+#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
+#define HWA_CC_PLL     2
 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
 #define HWA_CC_PLL     2
 #else
@@ -186,8 +194,7 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 
 #ifdef CONFIG_QE
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
        sysInfo->freqQE =  sysInfo->freqSystemBus;
 #else
        qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
@@ -229,6 +236,13 @@ void get_sys_info (sys_info_t * sysInfo)
                sysInfo->freqLocalBus = lcrr_div;
        }
 #endif
+
+#if defined(CONFIG_FSL_IFC)
+       ccr = in_be32(&ifc_regs->ifc_ccr);
+       ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+       sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
+#endif
 }