+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
*
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <cpu_func.h>
+#include <clock_legacy.h>
#include <ppc_asm.tmpl>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
-#endif
/* --------------------------------------------------------------- */
void get_sys_info(sys_info_t *sys_info)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
- struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
- u32 ccr;
-#endif
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
- volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+ volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
#ifdef CONFIG_HETROGENOUS_CLUSTERS
unsigned int dsp_cpu;
uint rcw_tmp1, rcw_tmp2;
#endif
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
- int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+ int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
#endif
__maybe_unused u32 svr;
[14] = 4, /* CC4 PPL / 4 */
};
uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
-#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
- defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
+#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
uint rcw_tmp;
#endif
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
- unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ unsigned long sysclk = get_board_sys_clk();
uint mem_pll_rat;
sys_info->freq_systembus = sysclk;
* are driven by differential sysclock.
*/
if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
- sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_ddrbus = get_board_sys_clk();
else
#endif
-#ifdef CONFIG_DDR_CLK_FREQ
- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
+ sys_info->freq_ddrbus = get_board_ddr_clk();
#else
sys_info->freq_ddrbus = sysclk;
#endif
* it uses 6.
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
- defined(CONFIG_PPC_T4080) || defined(CONFIG_ARCH_T2080) || \
- defined(CONFIG_ARCH_T2081)
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T2080)
svr = get_svr();
switch (SVR_SOC_VER(svr)) {
case SVR_T4240:
#endif
#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
- defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+ defined(CONFIG_ARCH_T2080)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
-#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#elif defined(CONFIG_ARCH_T1024)
#define FM1_CLK_SEL 0x00000007
#define FM1_CLK_SHIFT 0
#else
#define FM1_CLK_SHIFT 26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
-#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#if defined(CONFIG_ARCH_T1024)
rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
#else
rcw_tmp = in_be32(&gur->rcwsr[7]);
#endif
#endif
-#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
-#if defined(CONFIG_ARCH_T2080)
-#define ESDHC_CLK_SEL 0x00000007
-#define ESDHC_CLK_SHIFT 0
-#define ESDHC_CLK_RCWSR 15
-#else /* Support T1040 T1024 by now */
-#define ESDHC_CLK_SEL 0xe0000000
-#define ESDHC_CLK_SHIFT 29
-#define ESDHC_CLK_RCWSR 7
-#endif
- rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
- switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
- case 1:
- sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
- break;
- case 2:
- sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
- break;
- case 3:
- sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
- break;
-#if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
- case 4:
- sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
- break;
-#if defined(CONFIG_ARCH_T2080)
- case 5:
- sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
- break;
-#endif
- case 6:
- sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
- break;
- case 7:
- sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
- break;
-#endif
- default:
- sys_info->freq_sdhc = 0;
- printf("Error: Unknown SDHC peripheral clock select!\n");
- }
-#endif
#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
- sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_systembus = plat_ratio * get_board_sys_clk();
/* Divide before multiply to avoid integer
* overflow for processor speeds above 2GHz */
/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
sys_info->freq_ddrbus = sys_info->freq_systembus;
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
{
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
if (ddr_ratio != 0x7)
- sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
+ sys_info->freq_ddrbus = ddr_ratio * get_board_ddr_clk();
}
#endif
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
- sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_qe = qe_ratio * get_board_sys_clk();
#endif
#endif
#endif /* CONFIG_FSL_CORENET */
#if defined(CONFIG_FSL_LBC)
- uint lcrr_div;
-#if defined(CONFIG_SYS_LBC_LCRR)
- /* We will program LCRR to this value later */
- lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
- lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
-#endif
- if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-#if defined(CONFIG_FSL_CORENET)
- /* If this is corenet based SoC, bit-representation
- * for four times the clock divider values.
- */
- lcrr_div *= 4;
-#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
- !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
- /*
- * Yes, the entire PQ38 family use the same
- * bit-representation for twice the clock divider values.
- */
- lcrr_div *= 2;
-#endif
- sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
- } else {
- /* In case anyone cares what the unknown value is */
- sys_info->freq_localbus = lcrr_div;
- }
+ sys_info->freq_localbus = sys_info->freq_systembus /
+ CONFIG_SYS_FSL_LBC_CLK_DIV;
#endif
#if defined(CONFIG_FSL_IFC)
- ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
- ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
- sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+ sys_info->freq_localbus = sys_info->freq_systembus /
+ CONFIG_SYS_FSL_IFC_CLK_DIV;
#endif
}
-
-int get_clocks (void)
+int get_clocks(void)
{
sys_info_t sys_info;
#ifdef CONFIG_ARCH_MPC8544
- volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
-#endif
-#if defined(CONFIG_CPM2)
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
- uint sccr, dfbrg;
-
- /* set VCO = 4 * BRG */
- cpm->im_cpm_intctl.sccr &= 0xfffffffc;
- sccr = cpm->im_cpm_intctl.sccr;
- dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
+ volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85xx_GUTS_ADDR;
#endif
get_sys_info (&sys_info);
gd->cpu_clk = sys_info.freq_processor[0];
* for that SOC. This information is taken from application note
* AN2919.
*/
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
- defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
- defined(CONFIG_ARCH_P1022)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_ARCH_MPC8544)
/*
gd->arch.i2c2_clk = gd->arch.i2c1_clk;
#if defined(CONFIG_FSL_ESDHC)
-#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
- gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
-#else
-#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
+#if defined(CONFIG_ARCH_P1010)
gd->arch.sdhc_clk = gd->bus_clk;
#else
gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif
-#endif
#endif /* defined(CONFIG_FSL_ESDHC) */
-#if defined(CONFIG_CPM2)
- gd->arch.vco_out = 2*sys_info.freq_systembus;
- gd->arch.cpm_clk = gd->arch.vco_out / 2;
- gd->arch.scc_clk = gd->arch.vco_out / 4;
- gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
-#endif
-
if(gd->cpu_clk != 0) return (0);
else return (1);
}
* get_bus_freq
* return system bus freq in Hz
*********************************************/
-ulong get_bus_freq (ulong dummy)
+ulong get_bus_freq(ulong dummy)
{
return gd->bus_clk;
}
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