global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 1fe914a..31d0481 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -20,24 +20,20 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-
-#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
-#define CONFIG_SYS_FSL_NUM_CC_PLLS     6
-#endif
 /* --------------------------------------------------------------- */
 
 void get_sys_info(sys_info_t *sys_info)
 {
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_FSL_CORENET
-       volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+       volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR);
        unsigned int cpu;
 #ifdef CONFIG_HETROGENOUS_CLUSTERS
        unsigned int dsp_cpu;
        uint rcw_tmp1, rcw_tmp2;
 #endif
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
-       int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+       int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
 #endif
        __maybe_unused u32 svr;
 
@@ -75,7 +71,7 @@ void get_sys_info(sys_info_t *sys_info)
        uint rcw_tmp;
 #endif
        uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-       unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+       unsigned long sysclk = get_board_sys_clk();
        uint mem_pll_rat;
 
        sys_info->freq_systembus = sysclk;
@@ -102,7 +98,7 @@ void get_sys_info(sys_info_t *sys_info)
         * are driven by differential sysclock.
         */
        if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
-               sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+               sys_info->freq_ddrbus = get_board_sys_clk();
        else
 #endif
 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
@@ -526,7 +522,7 @@ void get_sys_info(sys_info_t *sys_info)
 
        plat_ratio = (gur->porpllsr) & 0x0000003e;
        plat_ratio >>= 1;
-       sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+       sys_info->freq_systembus = plat_ratio * get_board_sys_clk();
 
        /* Divide before multiply to avoid integer
         * overflow for processor speeds above 2GHz */
@@ -554,7 +550,7 @@ void get_sys_info(sys_info_t *sys_info)
 #else
        qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
                        >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
-       sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
+       sys_info->freq_qe = qe_ratio * get_board_sys_clk();
 #endif
 #endif
 
@@ -579,16 +575,7 @@ int get_clocks(void)
 {
        sys_info_t sys_info;
 #ifdef CONFIG_ARCH_MPC8544
-       volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
-#endif
-#if defined(CONFIG_CPM2)
-       volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-       uint sccr, dfbrg;
-
-       /* set VCO = 4 * BRG */
-       cpm->im_cpm_intctl.sccr &= 0xfffffffc;
-       sccr = cpm->im_cpm_intctl.sccr;
-       dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
+       volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85xx_GUTS_ADDR;
 #endif
        get_sys_info (&sys_info);
        gd->cpu_clk = sys_info.freq_processor[0];
@@ -635,13 +622,6 @@ int get_clocks(void)
 #endif
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
-#if defined(CONFIG_CPM2)
-       gd->arch.vco_out = 2*sys_info.freq_systembus;
-       gd->arch.cpm_clk = gd->arch.vco_out / 2;
-       gd->arch.scc_clk = gd->arch.vco_out / 4;
-       gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
-#endif
-
        if(gd->cpu_clk != 0) return (0);
        else return (1);
 }