powerpc/boot: Change the macro of Boot from SRIO and PCIE master module

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / p2041_ids.c

diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
index 112ea56..ef685fe 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
@@ -27,19 +27,25 @@
 #ifdef CONFIG_SYS_DPAA_QBMAN
 struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
        /* dqrr liodn, frame data liodn, liodn off, sdest */
-       SET_QP_INFO( 1,  2,  1, 0),
-       SET_QP_INFO( 3,  4,  2, 1),
-       SET_QP_INFO( 5,  6,  3, 2),
-       SET_QP_INFO( 7,  8,  4, 3),
-       SET_QP_INFO( 9, 10,  5, 4),
-       SET_QP_INFO( 0,  0,  0, 5),
-       SET_QP_INFO( 0,  0,  0, 6),
-       SET_QP_INFO( 0,  0,  0, 7),
-       SET_QP_INFO( 0,  0,  0, 0), /* for now sdest to 0 */
-       SET_QP_INFO( 0,  0,  0, 0), /* for now sdest to 0 */
+       SET_QP_INFO(1,  2,  1, 0),
+       SET_QP_INFO(3,  4,  2, 1),
+       SET_QP_INFO(5,  6,  3, 2),
+       SET_QP_INFO(7,  8,  4, 3),
+       SET_QP_INFO(9, 10,  5, 0),
+       SET_QP_INFO(11, 12,  6, 1),
+       SET_QP_INFO(13, 14,  7, 2),
+       SET_QP_INFO(15, 16,  8, 3),
+       SET_QP_INFO(17, 18,  9, 0), /* for now sdest to 0 */
+       SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
 };
 #endif
 
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+       SET_SRIO_LIODN_2(1, 199, 200),
+       SET_SRIO_LIODN_2(2, 201, 202),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+
 struct liodn_id_table liodn_tbl[] = {
 #ifdef CONFIG_SYS_DPAA_QBMAN
        SET_QMAN_LIODN(31),
@@ -56,9 +62,9 @@ struct liodn_id_table liodn_tbl[] = {
        SET_SATA_LIODN(1, 127),
        SET_SATA_LIODN(2, 128),
 
-       SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
-       SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
-       SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
+       SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
+       SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
+       SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
 
        SET_DMA_LIODN(1, 197),
        SET_DMA_LIODN(2, 198),
@@ -98,6 +104,17 @@ struct liodn_id_table sec_liodn_tbl[] = {
 };
 int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
 
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+       /* Set RMan block 0-3 liodn offset */
+       SET_RMAN_LIODN(0, 6),
+       SET_RMAN_LIODN(1, 7),
+       SET_RMAN_LIODN(2, 8),
+       SET_RMAN_LIODN(3, 9),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
 struct liodn_id_table liodn_bases[] = {
        [FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(64, 100),
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -106,4 +123,7 @@ struct liodn_id_table liodn_bases[] = {
 #ifdef CONFIG_SYS_DPAA_PME
        [FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(136, 172),
 #endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+       [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80),
+#endif
 };