global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / mp.c

diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index b0aa72e..f109ecb 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -4,13 +4,19 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <log.h>
+#include <asm/global_data.h>
 #include <asm/processor.h>
+#include <env.h>
 #include <ioports.h>
 #include <lmb.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
 #include <fsl_ddr_sdram.h>
+#include <linux/delay.h>
 #include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -44,7 +50,7 @@ int hold_cores_in_reset(int verbose)
 
 int cpu_reset(u32 nr)
 {
-       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+       volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
        out_be32(&pic->pir, 1 << nr);
        /* the dummy read works around an errata on early 85xx MP PICs */
        (void)in_be32(&pic->pir);
@@ -81,7 +87,7 @@ int cpu_status(u32 nr)
 #ifdef CONFIG_FSL_CORENET
 int cpu_disable(u32 nr)
 {
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        setbits_be32(&gur->coredisrl, 1 << nr);
 
@@ -89,7 +95,7 @@ int cpu_disable(u32 nr)
 }
 
 int is_core_disabled(int nr) {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 coredisrl = in_be32(&gur->coredisrl);
 
        return (coredisrl & (1 << nr));
@@ -97,7 +103,7 @@ int is_core_disabled(int nr) {
 #else
 int cpu_disable(u32 nr)
 {
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        switch (nr) {
        case 0:
@@ -115,7 +121,7 @@ int cpu_disable(u32 nr)
 }
 
 int is_core_disabled(int nr) {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 devdisr = in_be32(&gur->devdisr);
 
        switch (nr) {
@@ -137,7 +143,7 @@ static u8 boot_entry_map[4] = {
        BOOT_ENTRY_R3_LOWER,
 };
 
-int cpu_release(u32 nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char *const argv[])
 {
        u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
        u64 boot_addr;
@@ -161,7 +167,7 @@ int cpu_release(u32 nr, int argc, char * const argv[])
        for (i = 1; i < 3; i++) {
                if (argv[i][0] != '-') {
                        u8 entry = boot_entry_map[i];
-                       val = simple_strtoul(argv[i], NULL, 16);
+                       val = hextoul(argv[i], NULL);
                        table[entry] = val;
                }
        }
@@ -258,10 +264,10 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
        u32 mask = cpu_mask();
        struct law_entry e;
 
-       gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
-       rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
-       pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+       gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+       ccm = (void *)(CFG_SYS_FSL_CORENET_CCM_ADDR);
+       rcpm = (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
+       pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
 
        whoami = in_be32(&pic->whoami);
        cpu_up_mask = 1 << whoami;
@@ -330,9 +336,9 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
        u32 up, cpu_up_mask, whoami;
        u32 *table = (u32 *)&__spin_table;
        volatile u32 bpcr;
-       volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+       volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
        u32 devdisr;
        int timeout = 10;
 
@@ -450,18 +456,18 @@ void setup_mp(void)
        flush_cache(bootpg, 4096);
 
        /* look for the tlb covering the reset page, there better be one */
-       i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
+       i = find_tlb_idx((void *)BPTR_VIRT_ADDR, 1);
 
        /* we found a match */
        if (i != -1) {
                /* map reset page to bootpg so we can copy code there */
                disable_tlb(i);
 
-               set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
+               set_tlb(1, BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
                        0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
 
-               memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
+               memcpy((void *)BPTR_VIRT_ADDR, (void *)fixup, 4096);
 
                plat_mp_up(bootpg_map, pagesize);
        } else {