85xx: Add support for not releasing secondary cores via 'mp_holdoff'

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / mp.c

diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index ddbc221..a019b1b 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -36,9 +36,30 @@ u32 get_my_id()
        return mfspr(SPRN_PIR);
 }
 
+/*
+ * Determine if U-Boot should keep secondary cores in reset, or let them out
+ * of reset and hold them in a spinloop
+ */
+int hold_cores_in_reset(int verbose)
+{
+       const char *s = getenv("mp_holdoff");
+
+       /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
+       if (s && (*s == 'y' || *s == 'Y' || *s == '1')) {
+               if (verbose) {
+                       puts("Secondary cores are being held in reset.\n");
+                       puts("See 'mp_holdoff' environment variable\n");
+               }
+
+               return 1;
+       }
+
+       return 0;
+}
+
 int cpu_reset(int nr)
 {
-       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
        out_be32(&pic->pir, 1 << nr);
        /* the dummy read works around an errata on early 85xx MP PICs */
        (void)in_be32(&pic->pir);
@@ -51,6 +72,9 @@ int cpu_status(int nr)
 {
        u32 *table, id = get_my_id();
 
+       if (hold_cores_in_reset(1))
+               return 0;
+
        if (nr == id) {
                table = (u32 *)get_spin_virt_addr();
                printf("table base @ 0x%p\n", table);
@@ -77,6 +101,13 @@ int cpu_disable(int nr)
 
        return 0;
 }
+
+int is_core_disabled(int nr) {
+       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 coredisrl = in_be32(&gur->coredisrl);
+
+       return (coredisrl & (1 << nr));
+}
 #else
 int cpu_disable(int nr)
 {
@@ -96,6 +127,22 @@ int cpu_disable(int nr)
 
        return 0;
 }
+
+int is_core_disabled(int nr) {
+       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 devdisr = in_be32(&gur->devdisr);
+
+       switch (nr) {
+       case 0:
+               return (devdisr & MPC85xx_DEVDISR_CPU0);
+       case 1:
+               return (devdisr & MPC85xx_DEVDISR_CPU1);
+       default:
+               printf("Invalid cpu number for disable %d\n", nr);
+       }
+
+       return 0;
+}
 #endif
 
 static u8 boot_entry_map[4] = {
@@ -110,6 +157,9 @@ int cpu_release(int nr, int argc, char * const argv[])
        u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
        u64 boot_addr;
 
+       if (hold_cores_in_reset(1))
+               return 0;
+
        if (nr == get_my_id()) {
                printf("Invalid to release the boot core.\n\n");
                return 1;
@@ -184,7 +234,7 @@ static void plat_mp_up(unsigned long bootpg)
        gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
        rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
-       pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+       pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 
        nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
 
@@ -249,7 +299,7 @@ static void plat_mp_up(unsigned long bootpg)
        volatile u32 bpcr;
        volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
        u32 devdisr;
        int timeout = 10;
 
@@ -330,6 +380,10 @@ void setup_mp(void)
        ulong fixup = (ulong)&__secondary_start_page;
        u32 bootpg = determine_mp_bootpg();
 
+       /* Some OSes expect secondary cores to be held in reset */
+       if (hold_cores_in_reset(0))
+               return;
+
        /* Store the bootpg's SDRAM address for use by secondary CPU cores */
        __bootpg_addr = bootpg;