Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / fsl_corenet_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index e6b1b1b..5495dc5 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -489,7 +489,7 @@ static void wait_for_rstdone(unsigned int bank)
 }
 
 
-void __soc_serdes_init(void)
+static void __soc_serdes_init(void)
 {
        /* Allow for SoC-specific initialization in <SOC>_serdes.c  */
 };
@@ -714,9 +714,13 @@ void fsl_serdes_init(void)
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
                /*
-                * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for
-                * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or
-                * AURORA before the device is initialized.
+                * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
+                * for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
+                * or AURORA before the device is initialized.
+                *
+                * Note that this part of the SERDES-9 work-around is
+                * redundant if the work-around for A-4580 has already been
+                * applied via PBI.
                 */
                switch (lane_prtcl) {
                case SGMII_FM1_DTSEC1:
@@ -733,10 +737,12 @@ void fsl_serdes_init(void)
                case SRIO1:
                case SRIO2:
                case AURORA:
-                       clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
-                                       SRDS_TTLCR0_FLT_SEL_MASK,
-                                       SRDS_TTLCR0_FLT_SEL_750PPM |
-                                       SRDS_TTLCR0_PM_DIS);
+                       out_be32(&srds_regs->lane[idx].ttlcr0,
+                                SRDS_TTLCR0_FLT_SEL_KFR_26 |
+                                SRDS_TTLCR0_FLT_SEL_KPH_28 |
+                                SRDS_TTLCR0_FLT_SEL_750PPM |
+                                SRDS_TTLCR0_FREQOVD_EN);
+                       break;
                default:
                        break;
                }