powerpc: mpc85xx: Move set_liodns, setup_portals to common boot seq

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b237505..8c6b678 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -19,14 +19,21 @@
 #include <asm/io.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
-#include <asm/fsl_errata.h>
+#include <fsl_errata.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
+#ifdef CONFIG_FSL_CORENET
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#endif
 #include <fsl_usb.h>
 #include <hwconfig.h>
 #include <linux/compiler.h>
 #include "mp.h"
+#ifdef CONFIG_FSL_CAAM
+#include <fsl_sec.h>
+#endif
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
 #include <errno.h>
@@ -254,12 +261,36 @@ static void enable_tdm_law(void)
 void enable_cpc(void)
 {
        int i;
+       int ret;
        u32 size = 0;
-
+       u32 cpccfg0;
+       char buffer[HWCONFIG_BUFFER_SIZE];
+       char cpc_subarg[16];
+       bool have_hwconfig = false;
+       int cpc_args = 0;
        cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
+       /* Extract hwconfig from environment */
+       ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+       if (ret > 0) {
+               /*
+                * If "en_cpc" is not defined in hwconfig then by default all
+                * cpcs are enable. If this config is defined then individual
+                * cpcs which have to be enabled should also be defined.
+                * e.g en_cpc:cpc1,cpc2;
+                */
+               if (hwconfig_f("en_cpc", buffer))
+                       have_hwconfig = true;
+       }
+
        for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
-               u32 cpccfg0 = in_be32(&cpc->cpccfg0);
+               if (have_hwconfig) {
+                       sprintf(cpc_subarg, "cpc%u", i + 1);
+                       cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
+                       if (cpc_args == 0)
+                               continue;
+               }
+               cpccfg0 = in_be32(&cpc->cpccfg0);
                size += CPC_CFG0_SZ_K(cpccfg0);
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
@@ -397,9 +428,9 @@ void fsl_erratum_a007212_workaround(void)
 
 ulong cpu_init_f(void)
 {
-       ulong flag = 0;
        extern void m8560_cpm_reset (void);
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
+       (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_SECURE_BOOT)
@@ -431,6 +462,12 @@ ulong cpu_init_f(void)
 #if defined(CONFIG_SYS_CPC_REINIT_F)
        disable_cpc_sram();
 #endif
+
+#if defined(CONFIG_FSL_CORENET)
+       /* Put PAMU in bypass mode */
+       out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
+#endif
+
 #endif
 
 #ifdef CONFIG_CPM2
@@ -465,18 +502,11 @@ ulong cpu_init_f(void)
        in_be32(&gur->dcsrcr);
 #endif
 
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-#ifdef CONFIG_DEEP_SLEEP
-       /* disable the console if boot from deep sleep */
-       if (in_be32(&gur->scrtsr[0]) & (1 << 3))
-               flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
-#endif
-#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
        fsl_erratum_a007212_workaround();
 #endif
 
-       return flag;
+       return 0;
 }
 
 /* Implement a dummy function for those platforms w/o SERDES */
@@ -762,6 +792,13 @@ int cpu_init_r(void)
                spin_table_compat = 1;
 #endif
 
+#ifdef CONFIG_FSL_CORENET
+       set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+       setup_portals();
+#endif
+#endif
+
        l2cache_init();
 #if defined(CONFIG_RAMBOOT_PBL)
        disable_cpc_sram();
@@ -779,7 +816,7 @@ int cpu_init_r(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 #define MCFGR_AXIPIPE 0x000000f0
        if (IS_SVR_REV(svr, 1, 0))
-               clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
+               sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
 #endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
@@ -914,6 +951,10 @@ int cpu_init_r(void)
        fman_enet_init();
 #endif
 
+#ifdef CONFIG_FSL_CAAM
+       sec_init();
+#endif
+
 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
        /*
         * For P1022/1013 Rev1.0 silicon, after power on SATA host