Merge branch '2021-08-31-kconfig-migrations-part2' into next

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 9f9eed1..cd32290 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -11,13 +11,17 @@
 #include <config.h>
 #include <common.h>
 #include <cpu_func.h>
+#include <clock_legacy.h>
+#include <init.h>
 #include <irq_func.h>
+#include <log.h>
 #include <time.h>
 #include <vsprintf.h>
 #include <watchdog.h>
 #include <command.h>
 #include <fsl_esdhc.h>
 #include <asm/cache.h>
+#include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <fsl_ifc.h>
@@ -27,6 +31,7 @@
 #include <asm/processor.h>
 #include <fsl_ddr_sdram.h>
 #include <asm/ppc.h>
+#include <linux/delay.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -48,7 +53,8 @@ int checkcpu (void)
        uint major, minor;
        struct cpu_type *cpu;
        char buf1[32], buf2[32];
-#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
+       defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
        ccsr_gur_t __iomem *gur =
                (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
@@ -66,12 +72,12 @@ int checkcpu (void)
                >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #else  /* CONFIG_FSL_CORENET */
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
        u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
                >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 #else
        u32 ddr_ratio = 0;
-#endif /* CONFIG_DDR_CLK_FREQ */
+#endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */
 #endif /* CONFIG_FSL_CORENET */
 
        unsigned int i, core, nr_cores = cpu_numcores();
@@ -294,11 +300,10 @@ int checkcpu (void)
 
 /* ------------------------------------------------------------------------- */
 
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 /* Everything after the first generation of PQ3 parts has RSTCR */
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
-       defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
        unsigned long val, msr;
 
        /*
@@ -374,7 +379,7 @@ watchdog_reset(void)
  * Initializes on-chip MMC controllers.
  * to override, implement board_mmc_init()
  */
-int cpu_mmc_init(bd_t *bis)
+int cpu_mmc_init(struct bd_info *bis)
 {
 #ifdef CONFIG_FSL_ESDHC
        return fsl_esdhc_mmc_init(bis);
@@ -391,7 +396,9 @@ int cpu_mmc_init(bd_t *bis)
 void print_reginfo(void)
 {
        print_tlbcam();
+#ifdef CONFIG_FSL_LAW
        print_laws();
+#endif
 #if defined(CONFIG_FSL_LBC)
        print_lbc_regs();
 #endif