Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 12e8e10..6274f92 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -77,6 +77,30 @@ int checkcpu (void)
        major = SVR_MAJ(svr);
        minor = SVR_MIN(svr);
 
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
+       if (SVR_SOC_VER(svr) == SVR_T4080) {
+               ccsr_rcpm_t *rcpm =
+                       (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+
+               setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
+                            FSL_CORENET_DEVDISR2_DTSEC1_9);
+               setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
+               setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
+
+               /* It needs SW to disable core4~7 as HW design sake on T4080 */
+               for (i = 4; i < 8; i++)
+                       cpu_disable(i);
+
+               /* request core4~7 into PH20 state, prior to entering PCL10
+                * state, all cores in cluster should be placed in PH20 state.
+                */
+               setbits_be32(&rcpm->pcph20setr, 0xf0);
+
+               /* put the 2nd cluster into PCL10 state */
+               setbits_be32(&rcpm->clpcl10setr, 1 << 1);
+       }
+#endif
+
        if (cpu_numcores() > 1) {
 #ifndef CONFIG_MP
                puts("Unicore software on multiprocessor system!!\n"
@@ -286,6 +310,14 @@ __weak unsigned long get_tbclk (void)
 
 
 #if defined(CONFIG_WATCHDOG)
+#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
+void
+init_85xx_watchdog(void)
+{
+       mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
+             TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
+}
+
 void
 reset_85xx_watchdog(void)
 {