* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
*/
#include <config.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/mmu.h>
-#include <fsl_ifc.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
#include <post.h>
#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
-/*
- * Default board reset function
- */
-static void
-__board_reset(void)
-{
- /* Do nothing */
-}
-void board_reset(void) __attribute__((weak, alias("__board_reset")));
-
int checkcpu (void)
{
sys_info_t sysinfo;
uint pvr, svr;
+ uint fam;
uint ver;
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
- ccsr_gur_t __iomem *gur =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif
-
- /*
- * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
- * mode. Previous platform use ddr ratio to do the same. This
- * information is only for display here.
- */
-#ifdef CONFIG_FSL_CORENET
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
- u32 ddr_sync = 0; /* only async mode is supported */
-#else
- u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
- >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
-#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
-#else /* CONFIG_FSL_CORENET */
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif /* CONFIG_FSL_CORENET */
#ifdef CONFIG_DDR_CLK_FREQ
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
+#ifdef CONFIG_FSL_CORENET
+ u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
+ >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
+#else
u32 ddr_ratio = 0;
-#endif /* CONFIG_DDR_CLK_FREQ */
#endif /* CONFIG_FSL_CORENET */
-
- unsigned int i, core, nr_cores = cpu_numcores();
- u32 mask = cpu_mask();
+#endif /* CONFIG_DDR_CLK_FREQ */
+ int i;
svr = get_svr();
major = SVR_MAJ(svr);
+#ifdef CONFIG_MPC8536
+ major &= 0x7; /* the msb of this nibble is a mfg code */
+#endif
minor = SVR_MIN(svr);
if (cpu_numcores() > 1) {
puts("CPU: ");
}
- cpu = gd->arch.cpu;
+ cpu = gd->cpu;
puts(cpu->name);
if (IS_E_PROCESSOR(svr))
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
pvr = get_pvr();
+ fam = PVR_FAM(pvr);
ver = PVR_VER(pvr);
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
printf("Core: ");
- switch(ver) {
- case PVR_VER_E500_V1:
- case PVR_VER_E500_V2:
- puts("e500");
- break;
- case PVR_VER_E500MC:
- puts("e500mc");
- break;
- case PVR_VER_E5500:
- puts("e5500");
- break;
- case PVR_VER_E6500:
- puts("e6500");
- break;
- default:
+ if (PVR_FAM(PVR_85xx)) {
+ switch(PVR_MEM(pvr)) {
+ case 0x1:
+ case 0x2:
+ puts("E500");
+ break;
+ case 0x3:
+ puts("E500MC");
+ break;
+ case 0x4:
+ puts("E5500");
+ break;
+ default:
+ puts("Unknown");
+ break;
+ }
+ } else {
puts("Unknown");
- break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
- if (nr_cores > CONFIG_MAX_CPUS) {
- panic("\nUnexpected number of cores: %d, max is %d\n",
- nr_cores, CONFIG_MAX_CPUS);
- }
-
get_sys_info(&sysinfo);
puts("Clock Configuration:");
- for_each_cpu(i, core, nr_cores, mask) {
+ for (i = 0; i < cpu_numcores(); i++) {
if (!(i & 3))
printf ("\n ");
- printf("CPU%d:%-4s MHz, ", core,
- strmhz(buf1, sysinfo.freq_processor[core]));
+ printf("CPU%d:%-4s MHz, ",
+ i,strmhz(buf1, sysinfo.freqProcessor[i]));
}
- printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
- printf("\n");
+ printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
#ifdef CONFIG_FSL_CORENET
if (ddr_sync == 1) {
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Synchronous), ",
- strmhz(buf1, sysinfo.freq_ddrbus/2),
- strmhz(buf2, sysinfo.freq_ddrbus));
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
} else {
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Asynchronous), ",
- strmhz(buf1, sysinfo.freq_ddrbus/2),
- strmhz(buf2, sysinfo.freq_ddrbus));
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
}
#else
switch (ddr_ratio) {
case 0x0:
printf(" DDR:%-4s MHz (%s MT/s data rate), ",
- strmhz(buf1, sysinfo.freq_ddrbus/2),
- strmhz(buf2, sysinfo.freq_ddrbus));
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
break;
case 0x7:
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Synchronous), ",
- strmhz(buf1, sysinfo.freq_ddrbus/2),
- strmhz(buf2, sysinfo.freq_ddrbus));
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
break;
default:
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Asynchronous), ",
- strmhz(buf1, sysinfo.freq_ddrbus/2),
- strmhz(buf2, sysinfo.freq_ddrbus));
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
break;
}
#endif
#if defined(CONFIG_FSL_LBC)
- if (sysinfo.freq_localbus > LCRR_CLKDIV) {
- printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
+ if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
+ printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
} else {
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
- sysinfo.freq_localbus);
+ sysinfo.freqLocalBus);
}
#endif
-#if defined(CONFIG_FSL_IFC)
- printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
-#endif
-
#ifdef CONFIG_CPM2
- printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
+ printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
#endif
#ifdef CONFIG_QE
- printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
+ printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i + 1,
- strmhz(buf1, sysinfo.freq_fman[i]));
+ strmhz(buf1, sysinfo.freqFMan[i]));
}
#endif
-#ifdef CONFIG_SYS_DPAA_QBMAN
- printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
-#endif
-
#ifdef CONFIG_SYS_DPAA_PME
- printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
+ printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
#endif
- puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
-
-#ifdef CONFIG_FSL_CORENET
- /* Display the RCW, so that no one gets confused as to what RCW
- * we're actually using for this boot.
- */
- puts("Reset Configuration Word (RCW):");
- for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
- u32 rcw = in_be32(&gur->rcwsr[i]);
-
- if ((i % 4) == 0)
- printf("\n %08x:", i * 4);
- printf(" %08x", rcw);
- }
- puts("\n");
-#endif
+ puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
return 0;
}
mtspr(DBCR0,val);
#else
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- /* Attempt board-specific reset */
- board_reset();
-
- /* Next try asserting HRESET_REQ */
- out_be32(&gur->rstcr, 0x2);
+ out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */
udelay(100);
#endif
/*
* Get timebase clock frequency
*/
-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif
unsigned long get_tbclk (void)
{
- unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
-
- return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
+#ifdef CONFIG_FSL_CORENET
+ return (gd->bus_clk + 8) / 16;
+#else
+ return (gd->bus_clk + 4UL)/8UL;
+#endif
}
#if defined(CONFIG_WATCHDOG)
void
-reset_85xx_watchdog(void)
+watchdog_reset(void)
{
- /*
- * Clear TSR(WIS) bit by writing 1
- */
- mtspr(SPRN_TSR, TSR_WIS);
+ int re_enable = disable_interrupts();
+ reset_85xx_watchdog();
+ if (re_enable) enable_interrupts();
}
void
-watchdog_reset(void)
+reset_85xx_watchdog(void)
{
- int re_enable = disable_interrupts();
-
- reset_85xx_watchdog();
- if (re_enable)
- enable_interrupts();
+ /*
+ * Clear TSR(WIS) bit by writing 1
+ */
+ unsigned long val;
+ val = mfspr(SPRN_TSR);
+ val |= TSR_WIS;
+ mtspr(SPRN_TSR, val);
}
#endif /* CONFIG_WATCHDOG */
/*
* Print out the state of various machine registers.
- * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
- * parameters for IFC and TLBs
+ * Currently prints out LAWs, BR0/OR0, and TLBs
*/
void mpc85xx_reginfo(void)
{
#if defined(CONFIG_FSL_LBC)
print_lbc_regs();
#endif
-#ifdef CONFIG_FSL_IFC
- print_ifc_regs();
-#endif
}
/* Common ddr init for non-corenet fsl 85xx platforms */
#ifndef CONFIG_FSL_CORENET
-#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
- !defined(CONFIG_SYS_INIT_L2_ADDR)
-phys_size_t initdram(int board_type)
-{
-#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
- return fsl_ddr_sdram_size();
-#else
- return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-#endif
-}
-#else /* CONFIG_SYS_RAMBOOT */
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
}
#endif
-#if defined(CONFIG_SPD_EEPROM) || \
- defined(CONFIG_DDR_SPD) || \
- defined(CONFIG_SYS_DDR_RAW_TIMING)
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
dram_size = fsl_ddr_sdram();
#else
dram_size = fixed_sdram();
lbc_sdram_init();
#endif
- debug("DDR: ");
+ puts("DDR: ");
return dram_size;
}
-#endif /* CONFIG_SYS_RAMBOOT */
#endif
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
unsigned int
setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
-void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
-
static void dump_spd_ddr_reg(void)
{
int i, j, k, m;
u8 *p_8;
u32 *p_32;
- struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+ ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
generic_spd_eeprom_t
spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
switch (i) {
case 0:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
case 1:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
- break;
-#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
- case 2:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
- break;
-#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
- case 3:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+ ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
break;
#endif
default:
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
puts("\n");
- for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
+ for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
m = 0;
printf("%6d (0x%04x)", k * 4, k * 4);
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
unsigned long epn;
u32 tsize, valid, ptr;
+ phys_addr_t rpn = 0;
int ddr_esel;
- clear_ddr_tlbs_phys(p_addr, size>>20);
+ ptr = vstart;
+
+ while (ptr < (vstart + size)) {
+ ddr_esel = find_tlb_idx((void *)ptr, 1);
+ if (ddr_esel != -1) {
+ read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
+ disable_tlb(ddr_esel);
+ }
+ ptr += TSIZE_TO_BYTES(tsize);
+ }
/* Setup new tlb to cover the physical address */
setup_ddr_tlbs_phys(p_addr, size>>20);
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