powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / Kconfig

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 4878eed..b0f34b6 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -330,7 +330,9 @@ endchoice
 config ARCH_B4420
        bool
        select E500MC
+       select E6500
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A004477
        select SYS_FSL_ERRATUM_A005871
        select SYS_FSL_ERRATUM_A006379
@@ -343,13 +345,17 @@ config ARCH_B4420
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_B4860
        bool
        select E500MC
+       select E6500
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A004477
        select SYS_FSL_ERRATUM_A005871
        select SYS_FSL_ERRATUM_A006379
@@ -359,15 +365,19 @@ config ARCH_B4860
        select SYS_FSL_ERRATUM_A007075
        select SYS_FSL_ERRATUM_A007186
        select SYS_FSL_ERRATUM_A007212
+       select SYS_FSL_ERRATUM_A007907
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_BSC9131
        bool
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004477
        select SYS_FSL_ERRATUM_A005125
        select SYS_FSL_ERRATUM_ESDHC111
@@ -379,6 +389,7 @@ config ARCH_BSC9131
 config ARCH_BSC9132
        bool
        select FSL_LAW
+       select SYS_FSL_DDR_VER_46
        select SYS_FSL_ERRATUM_A004477
        select SYS_FSL_ERRATUM_A005125
        select SYS_FSL_ERRATUM_A005434
@@ -394,6 +405,7 @@ config ARCH_BSC9132
 config ARCH_C29X
        bool
        select FSL_LAW
+       select SYS_FSL_DDR_VER_46
        select SYS_FSL_ERRATUM_A005125
        select SYS_FSL_ERRATUM_ESDHC111
        select SYS_FSL_HAS_DDR3
@@ -639,6 +651,7 @@ config ARCH_P2041
        select SYS_FSL_ERRATUM_USB14
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
 
@@ -646,6 +659,7 @@ config ARCH_P3041
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004510
        select SYS_FSL_ERRATUM_A004849
        select SYS_FSL_ERRATUM_A005812
@@ -660,6 +674,7 @@ config ARCH_P3041
        select SYS_FSL_ERRATUM_USB14
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
 
@@ -667,6 +682,7 @@ config ARCH_P4080
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004510
        select SYS_FSL_ERRATUM_A004580
        select SYS_FSL_ERRATUM_A004849
@@ -692,6 +708,7 @@ config ARCH_P4080
        select SYS_P4080_ERRATUM_SERDES_A005
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
 
@@ -699,6 +716,7 @@ config ARCH_P5020
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004510
        select SYS_FSL_ERRATUM_A006261
        select SYS_FSL_ERRATUM_DDR_A003
@@ -709,13 +727,16 @@ config ARCH_P5020
        select SYS_FSL_ERRATUM_USB14
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_P5040
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004510
        select SYS_FSL_ERRATUM_A004699
        select SYS_FSL_ERRATUM_A005812
@@ -726,8 +747,10 @@ config ARCH_P5040
        select SYS_FSL_ERRATUM_USB14
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_QEMU_E500
        bool
@@ -736,6 +759,7 @@ config ARCH_T1023
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
@@ -743,6 +767,7 @@ config ARCH_T1023
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5
 
@@ -750,6 +775,7 @@ config ARCH_T1024
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
@@ -757,6 +783,7 @@ config ARCH_T1024
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5
 
@@ -764,6 +791,7 @@ config ARCH_T1040
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008044
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A009663
@@ -772,6 +800,7 @@ config ARCH_T1040
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5
 
@@ -779,6 +808,7 @@ config ARCH_T1042
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008044
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A009663
@@ -787,28 +817,36 @@ config ARCH_T1042
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5
 
 config ARCH_T2080
        bool
        select E500MC
+       select E6500
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A006379
        select SYS_FSL_ERRATUM_A006593
        select SYS_FSL_ERRATUM_A007186
        select SYS_FSL_ERRATUM_A007212
+       select SYS_FSL_ERRATUM_A007907
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_ESDHC111
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_T2081
        bool
        select E500MC
+       select E6500
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A006379
        select SYS_FSL_ERRATUM_A006593
        select SYS_FSL_ERRATUM_A007186
@@ -817,13 +855,17 @@ config ARCH_T2081
        select SYS_FSL_ERRATUM_ESDHC111
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_T4160
        bool
        select E500MC
+       select E6500
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A004468
        select SYS_FSL_ERRATUM_A005871
        select SYS_FSL_ERRATUM_A006379
@@ -833,13 +875,17 @@ config ARCH_T4160
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_T4240
        bool
        select E500MC
+       select E6500
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A004468
        select SYS_FSL_ERRATUM_A005871
        select SYS_FSL_ERRATUM_A006261
@@ -847,11 +893,14 @@ config ARCH_T4240
        select SYS_FSL_ERRATUM_A006593
        select SYS_FSL_ERRATUM_A007186
        select SYS_FSL_ERRATUM_A007798
+       select SYS_FSL_ERRATUM_A007907
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config BOOKE
        bool
@@ -868,6 +917,11 @@ config E500MC
        help
                Enble PowerPC E500MC core
 
+config E6500
+       bool
+       help
+               Enable PowerPC E6500 core
+
 config FSL_LAW
        bool
        help
@@ -1030,6 +1084,9 @@ config SYS_FSL_ERRATUM_A007212
 config SYS_FSL_ERRATUM_A007798
        bool
 
+config SYS_FSL_ERRATUM_A007907
+       bool
+
 config SYS_FSL_ERRATUM_A008044
        bool
 
@@ -1104,6 +1161,12 @@ config SYS_P4080_ERRATUM_SERDES_A001
 config SYS_P4080_ERRATUM_SERDES_A005
        bool
 
+config SYS_FSL_QORIQ_CHASSIS1
+       bool
+
+config SYS_FSL_QORIQ_CHASSIS2
+       bool
+
 config SYS_FSL_NUM_LAWS
        int "Number of local access windows"
        depends on FSL_LAW
@@ -1148,6 +1211,11 @@ config SYS_FSL_NUM_LAWS
                Number of local access windows. This is fixed per SoC.
                If not sure, do not change.
 
+config SYS_FSL_THREADS_PER_CORE
+       int
+       default 2 if E6500
+       default 1
+
 config SYS_NUM_TLBCAMS
        int "Number of TLB CAM entries"
        default 64 if E500MC
@@ -1156,6 +1224,9 @@ config SYS_NUM_TLBCAMS
                Number of TLB CAM entries for Book-E chips. 64 for E500MC,
                16 for other E500 SoCs.
 
+config SYS_PPC64
+       bool
+
 config SYS_PPC_E500_USE_DEBUG_TLB
        bool