powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / Kconfig

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 1e97c69..b0f34b6 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -348,6 +348,7 @@ config ARCH_B4420
        select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_B4860
        bool
@@ -364,12 +365,14 @@ config ARCH_B4860
        select SYS_FSL_ERRATUM_A007075
        select SYS_FSL_ERRATUM_A007186
        select SYS_FSL_ERRATUM_A007212
+       select SYS_FSL_ERRATUM_A007907
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
        select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_BSC9131
        bool
@@ -727,6 +730,7 @@ config ARCH_P5020
        select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_P5040
        bool
@@ -746,6 +750,7 @@ config ARCH_P5040
        select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_QEMU_E500
        bool
@@ -826,6 +831,7 @@ config ARCH_T2080
        select SYS_FSL_ERRATUM_A006593
        select SYS_FSL_ERRATUM_A007186
        select SYS_FSL_ERRATUM_A007212
+       select SYS_FSL_ERRATUM_A007907
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_ESDHC111
        select SYS_FSL_HAS_DDR3
@@ -833,6 +839,7 @@ config ARCH_T2080
        select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_T2081
        bool
@@ -851,6 +858,7 @@ config ARCH_T2081
        select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_T4160
        bool
@@ -870,6 +878,7 @@ config ARCH_T4160
        select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_T4240
        bool
@@ -884,12 +893,14 @@ config ARCH_T4240
        select SYS_FSL_ERRATUM_A006593
        select SYS_FSL_ERRATUM_A007186
        select SYS_FSL_ERRATUM_A007798
+       select SYS_FSL_ERRATUM_A007907
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
        select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config BOOKE
        bool
@@ -1073,6 +1084,9 @@ config SYS_FSL_ERRATUM_A007212
 config SYS_FSL_ERRATUM_A007798
        bool
 
+config SYS_FSL_ERRATUM_A007907
+       bool
+
 config SYS_FSL_ERRATUM_A008044
        bool
 
@@ -1210,6 +1224,9 @@ config SYS_NUM_TLBCAMS
                Number of TLB CAM entries for Book-E chips. 64 for E500MC,
                16 for other E500 SoCs.
 
+config SYS_PPC64
+       bool
+
 config SYS_PPC_E500_USE_DEBUG_TLB
        bool