This enables the 'errata' command which displays a list of errata
work-arounds which are enabled for the current board.
+config FSL_PREPBL_ESDHC_BOOT_SECTOR
+ bool "Generate QorIQ pre-PBL eSDHC boot sector"
+ depends on MPC85xx
+ depends on SYS_EXTRA_OPTIONS = SDCARD
+ help
+ With this option final image would have prepended QorIQ pre-PBL eSDHC
+ boot sector suitable for SD card images. This boot sector instruct
+ BootROM to configure L2 SRAM and eSDHC then load image from SD card
+ into L2 SRAM and finally jump to image entry point.
+
+ This is alternative to Freescale boot_format tool, but works only for
+ SD card images and only for L2 SRAM booting. U-Boot images generated
+ with this option should not passed to boot_format tool.
+
+ For other configuration like booting from eSPI or configuring SDRAM
+ please use Freescale boot_format tool without this option. See file
+ doc/README.mpc85xx-sd-spi-boot
+
+config FSL_PREPBL_ESDHC_BOOT_SECTOR_START
+ int "QorIQ pre-PBL eSDHC boot sector start offset"
+ depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
+ range 0 23
+ default 0
+ help
+ QorIQ pre-PBL eSDHC boot sector may be located on one of the first
+ 24 SD card sectors. Select SD card sector on which final U-Boot
+ image (with this boot sector) would be installed.
+
+ By default first SD card sector (0) is used. But this may be changed
+ to allow installing U-Boot image on some partition (with fixed start
+ sector).
+
+ Please note that any sector on SD card prior this boot sector must
+ not contain ASCII "BOOT" bytes at sector offset 0x40.
+
+config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
+ int "Relative data sector for QorIQ pre-PBL eSDHC boot sector"
+ depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
+ default 1
+ range 1 8388607
+ help
+ Select data sector from the beginning of QorIQ pre-PBL eSDHC boot
+ sector on which would be stored raw U-Boot image.
+
+ By default is it second sector (1) which is the first available free
+ sector (on the first sector is stored boot sector). It can be any
+ sector number which offset in bytes can be expressed by 32-bit number.
+
+ In case this final U-Boot image (with this boot sector) is put on
+ the FAT32 partition into reserved boot area, this data sector needs
+ to be at least 2 (third sector) because FAT32 use second sector for
+ its data.
+
choice
prompt "Target select"
optional
select PHYS_64BIT
select ARCH_P3041
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_NGPIXIS
imply CMD_SATA
imply PANIC_HANG
select PHYS_64BIT
select ARCH_P4080
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_NGPIXIS
imply CMD_SATA
imply PANIC_HANG
select PHYS_64BIT
select ARCH_P5040
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_NGPIXIS
+ select SYS_FSL_RAID_ENGINE
imply CMD_SATA
imply PANIC_HANG
bool "Support P2041RDB"
select ARCH_P2041
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CORENET
select PHYS_64BIT
imply CMD_SATA
imply FSL_SATA
bool "Support qemu-ppce500"
select ARCH_QEMU_E500
select PHYS_64BIT
+ select SYS_RAMBOOT
imply OF_HAS_PRIOR_STAGE
config TARGET_T1024RDB
config TARGET_KMCENT2
bool "Support kmcent2"
select VENDOR_KM
+ select FSL_CORENET
endchoice
bool
select E500MC
select E6500
+ select FSL_CORENET
select FSL_LAW
+ select HETROGENOUS_CLUSTERS
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A005871
select SYS_FSL_ERRATUM_A006475
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007075
- select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB1_PHY_ENABLE
select SYS_PPC64
select FSL_IFC
imply CMD_EEPROM
bool
select E500MC
select E6500
+ select FSL_CORENET
select FSL_LAW
+ select HETROGENOUS_CLUSTERS
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A005871
select SYS_FSL_ERRATUM_A006475
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007075
- select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SRIO_LIODN
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB1_PHY_ENABLE
select SYS_PPC64
select FSL_IFC
imply CMD_EEPROM
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR1
select SYS_FSL_HAS_SEC
+ select SYS_FSL_RMU
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1010
bool
+ select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
select BTB
select FSL_LAW
select SYS_CACHE_SHIFT_5
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_USB1_PHY_ENABLE
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_IFC
imply CMD_EEPROM
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select FSL_ELBC
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+ select SYS_FSL_RMU
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2041
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_USB1_PHY_ENABLE
+ select SYS_FSL_USB2_PHY_ENABLE
select FSL_ELBC
imply CMD_NAND
config ARCH_P3041
bool
+ select BACKSIDE_L2_CACHE
select E500MC
+ select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_USB1_PHY_ENABLE
+ select SYS_FSL_USB2_PHY_ENABLE
select FSL_ELBC
imply CMD_NAND
imply CMD_SATA
config ARCH_P4080
bool
+ select BACKSIDE_L2_CACHE
select E500MC
+ select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_I2C_A004447
select SYS_FSL_ERRATUM_NMG_CPU_A011
select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_FSL_PCIE_COMPAT_P4080_PCIE
select SYS_P4080_ERRATUM_CPU22
select SYS_P4080_ERRATUM_PCIE_A003
select SYS_P4080_ERRATUM_SERDES8
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_RMU
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select FSL_ELBC
config ARCH_P5040
bool
+ select BACKSIDE_L2_CACHE
select E500MC
+ select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_USB1_PHY_ENABLE
+ select SYS_FSL_USB2_PHY_ENABLE
select SYS_PPC64
select FSL_ELBC
imply CMD_SATA
config ARCH_T1024
bool
+ select BACKSIDE_L2_CACHE
select E500MC
+ select E5500
+ select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SINGLE_SOURCE_CLK
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC
imply CMD_EEPROM
imply CMD_NAND
config ARCH_T1040
bool
+ select BACKSIDE_L2_CACHE
select E500MC
+ select E5500
+ select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SINGLE_SOURCE_CLK
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC
imply CMD_MTDPARTS
imply CMD_NAND
config ARCH_T1042
bool
+ select BACKSIDE_L2_CACHE
select E500MC
+ select E5500
+ select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SINGLE_SOURCE_CLK
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC
imply CMD_MTDPARTS
imply CMD_NAND
bool
select E500MC
select E6500
+ select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
- select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A007815
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SRIO_LIODN
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB_DUAL_PHY_ENABLE
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
bool
select E500MC
select E6500
+ select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006261
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
- select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
select SYS_FSL_ERRATUM_A007798
select SYS_FSL_ERRATUM_A007815
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SRIO_LIODN
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB_DUAL_PHY_ENABLE
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
help
Enble PowerPC E500MC core
+config E5500
+ bool
+
config E6500
bool
select BTB
help
Use Freescale common code for Local Access Window
-config NXP_ESBC
- bool "NXP_ESBC"
- help
- Enable Freescale Secure Boot feature. Normally selected
- by defconfig. If unsure, do not change.
+config HETROGENOUS_CLUSTERS
+ bool
config MAX_CPUS
int "Maximum number of CPUs permitted for MPC85xx"
if changed by pre-boot regime. The value here must match
the current value in SoC. If not sure, do not change.
+config A003399_NOR_WORKAROUND
+ bool
+ help
+ Enables a workaround for IFC erratum A003399. It is only required
+ during NOR boot.
+
+config A008044_WORKAROUND
+ bool
+ help
+ Enables a workaround for T1040/T1042 erratum A008044. It is only
+ required during NAND boot and valid for Rev 1.0 SoC revision
+
config SYS_FSL_ERRATUM_A004468
bool
config SYS_FSL_ERRATUM_A008044
bool
+ select A008044_WORKAROUND if MTD_RAW_NAND
config SYS_FSL_ERRATUM_CPC_A002
bool
config FSL_PCIE_RESET
bool
+config SYS_FSL_RAID_ENGINE
+ bool
+
+config SYS_FSL_RMU
+ bool
+
config SYS_FSL_QORIQ_CHASSIS1
bool
Number of local access windows. This is fixed per SoC.
If not sure, do not change.
+config SYS_FSL_CORES_PER_CLUSTER
+ int
+ depends on SYS_FSL_QORIQ_CHASSIS2
+ default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240
+ default 2 if ARCH_B4420
+ default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042
+
config SYS_FSL_THREADS_PER_CORE
int
+ depends on SYS_FSL_QORIQ_CHASSIS2
default 2 if E6500
default 1
Number of TLB CAM entries for Book-E chips. 64 for E500MC,
16 for other E500 SoCs.
+if HETROGENOUS_CLUSTERS
+
+config SYS_MAPLE
+ def_bool y
+
+config SYS_CPRI
+ def_bool y
+
+config PPC_CLUSTER_START
+ int
+ default 0
+
+config DSP_CLUSTER_START
+ int
+ default 1
+
+config SYS_CPRI_CLK
+ int
+ default 3
+
+config SYS_ULB_CLK
+ int
+ default 4
+
+config SYS_ETVPE_CLK
+ int
+ default 1
+endif
+
+config BACKSIDE_L2_CACHE
+ bool
+
config SYS_PPC64
bool
Defines divider of platform clock(clock input to
eLBC controller).
+config ENABLE_36BIT_PHYS
+ bool "Enable 36bit physical address space support"
+
+config SYS_BOOK3E_HV
+ bool "Category E.HV is supported"
+ depends on BOOKE
+
+config FSL_CORENET
+ bool
+ select SYS_FSL_CPC
+
+config FSL_NGPIXIS
+ bool
+
+config SYS_CPC_REINIT_F
+ bool
+ help
+ The CPC is configured as SRAM at the time of U-Boot entry and is
+ required to be re-initialized.
+
+config SYS_FSL_CPC
+ bool
+
+config SYS_CACHE_STASHING
+ bool "Enable cache stashing"
+
+config SYS_FSL_PCIE_COMPAT_P4080_PCIE
+ bool
+
+config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
+ bool
+
+config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
+ bool
+
+config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
+ bool
+
+config SYS_FSL_PCIE_COMPAT
+ string
+ depends on FSL_CORENET
+ default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
+ default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
+ default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
+ default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
+ help
+ Defines the string to utilize when trying to match PCIe device tree
+ nodes for the given platform.
+
+config SYS_FSL_SINGLE_SOURCE_CLK
+ bool
+
+config SYS_FSL_SRIO_LIODN
+ bool
+
+config SYS_FSL_TBCLK_DIV
+ int
+ default 32 if ARCH_P2041 || ARCH_P3041
+ default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
+ ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
+ ARCH_T1024 || ARCH_T2080
+ default 8
+ help
+ Defines the core time base clock divider ratio compared to the system
+ clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
+ be 16 or 32. The ratio varies from SoC to Soc.
+
+config SYS_FSL_USB1_PHY_ENABLE
+ bool
+
+config SYS_FSL_USB2_PHY_ENABLE
+ bool
+
+config SYS_FSL_USB_DUAL_PHY_ENABLE
+ bool
+
+config SYS_MPC85XX_NO_RESETVEC
+ bool "Discard resetvec section and move bootpg section up"
+ depends on MPC85xx
+ help
+ If this variable is specified, the section .resetvec is not kept and
+ the section .bootpg is placed in the previous 4k of the .text section.
+
+config SPL_SYS_MPC85XX_NO_RESETVEC
+ bool "Discard resetvec section and move bootpg section up, in SPL"
+ depends on MPC85xx && SPL
+ help
+ If this variable is specified, the section .resetvec is not kept and
+ the section .bootpg is placed in the previous 4k of the .text section,
+ of the SPL portion of the binary.
+
+config TPL_SYS_MPC85XX_NO_RESETVEC
+ bool "Discard resetvec section and move bootpg section up, in TPL"
+ depends on MPC85xx && TPL
+ help
+ If this variable is specified, the section .resetvec is not kept and
+ the section .bootpg is placed in the previous 4k of the .text section,
+ of the SPL portion of the binary.
+
config FSL_VIA
bool
source "board/freescale/t208xqds/Kconfig"
source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4rdb/Kconfig"
-source "board/keymile/Kconfig"
source "board/socrates/Kconfig"
endmenu
projects / platform / kernel / u-boot.git / blobdiff