powerpc: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board
[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / Kconfig
index 8cc82f8..6928851 100644 (file)
@@ -24,28 +24,6 @@ config TARGET_SOCRATES
        bool "Support socrates"
        select ARCH_MPC8544
 
-config TARGET_B4420QDS
-       bool "Support B4420QDS"
-       select ARCH_B4420
-       select SUPPORT_SPL
-       select PHYS_64BIT
-       imply PANIC_HANG
-
-config TARGET_B4860QDS
-       bool "Support B4860QDS"
-       select ARCH_B4860
-       select BOARD_LATE_INIT if CHAIN_OF_TRUST
-       select SUPPORT_SPL
-       select PHYS_64BIT
-       select FSL_DDR_INTERACTIVE if !SPL_BUILD
-       imply PANIC_HANG
-
-config TARGET_BSC9131RDB
-       bool "Support BSC9131RDB"
-       select ARCH_BSC9131
-       select SUPPORT_SPL
-       select BOARD_EARLY_INIT_F
-
 config TARGET_BSC9132QDS
        bool "Support BSC9132QDS"
        select ARCH_BSC9132
@@ -352,6 +330,7 @@ config TARGET_T2080QDS
        select PHYS_64BIT
        select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
        select FSL_DDR_INTERACTIVE
+       imply CMD_SATA
 
 config TARGET_T2080RDB
        bool "Support T2080RDB"
@@ -360,7 +339,6 @@ config TARGET_T2080RDB
        select SUPPORT_SPL
        select PHYS_64BIT
        imply CMD_SATA
-       imply FSL_SATA
        imply PANIC_HANG
 
 config TARGET_T2081QDS
@@ -996,6 +974,7 @@ config ARCH_T1023
        select FSL_LAW
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008378
+       select SYS_FSL_ERRATUM_A008109
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_ESDHC111
@@ -1016,6 +995,7 @@ config ARCH_T1024
        select FSL_LAW
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008378
+       select SYS_FSL_ERRATUM_A008109
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_ESDHC111
@@ -1038,6 +1018,7 @@ config ARCH_T1040
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008044
        select SYS_FSL_ERRATUM_A008378
+       select SYS_FSL_ERRATUM_A008109
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_ESDHC111
@@ -1061,6 +1042,7 @@ config ARCH_T1042
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008044
        select SYS_FSL_ERRATUM_A008378
+       select SYS_FSL_ERRATUM_A008109
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_ESDHC111
@@ -1089,6 +1071,7 @@ config ARCH_T2080
        select SYS_FSL_ERRATUM_A007212
        select SYS_FSL_ERRATUM_A007815
        select SYS_FSL_ERRATUM_A007907
+       select SYS_FSL_ERRATUM_A008109
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_ESDHC111
        select FSL_PCIE_RESET
@@ -1099,8 +1082,10 @@ config ARCH_T2080
        select SYS_FSL_SEC_COMPAT_4
        select SYS_PPC64
        select FSL_IFC
+       imply CMD_SATA
        imply CMD_NAND
        imply CMD_REGINFO
+       imply FSL_SATA
 
 config ARCH_T2081
        bool
@@ -1165,6 +1150,7 @@ config ARCH_T4240
        select SYS_FSL_ERRATUM_A007798
        select SYS_FSL_ERRATUM_A007815
        select SYS_FSL_ERRATUM_A007907
+       select SYS_FSL_ERRATUM_A008109
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
@@ -1587,8 +1573,6 @@ config SYS_FSL_LBC_CLK_DIV
                Defines divider of platform clock(clock input to
                eLBC controller).
 
-source "board/freescale/b4860qds/Kconfig"
-source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
 source "board/freescale/c29xpcie/Kconfig"
 source "board/freescale/corenet_ds/Kconfig"