Merge git://git.denx.de/u-boot-mpc85xx

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / Kconfig

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 4878eed..38ea4c1 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -25,6 +25,7 @@ config TARGET_B4420QDS
 config TARGET_B4860QDS
        bool "Support B4860QDS"
        select ARCH_B4860
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
@@ -32,15 +33,19 @@ config TARGET_BSC9131RDB
        bool "Support BSC9131RDB"
        select ARCH_BSC9131
        select SUPPORT_SPL
+       select BOARD_EARLY_INIT_F
 
 config TARGET_BSC9132QDS
        bool "Support BSC9132QDS"
        select ARCH_BSC9132
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
+       select BOARD_EARLY_INIT_F
 
 config TARGET_C29XPCIE
        bool "Support C29XPCIE"
        select ARCH_C29X
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select SUPPORT_TPL
        select PHYS_64BIT
@@ -49,21 +54,25 @@ config TARGET_P3041DS
        bool "Support P3041DS"
        select PHYS_64BIT
        select ARCH_P3041
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
 
 config TARGET_P4080DS
        bool "Support P4080DS"
        select PHYS_64BIT
        select ARCH_P4080
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
 
 config TARGET_P5020DS
        bool "Support P5020DS"
        select PHYS_64BIT
        select ARCH_P5020
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
 
 config TARGET_P5040DS
        bool "Support P5040DS"
        select PHYS_64BIT
        select ARCH_P5040
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
 
 config TARGET_MPC8536DS
        bool "Support MPC8536DS"
@@ -112,12 +121,14 @@ config TARGET_MPC8572DS
 config TARGET_P1010RDB_PA
        bool "Support P1010RDB_PA"
        select ARCH_P1010
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select SUPPORT_TPL
 
 config TARGET_P1010RDB_PB
        bool "Support P1010RDB_PB"
        select ARCH_P1010
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select SUPPORT_TPL
 
@@ -186,6 +197,7 @@ config TARGET_P1_TWR
 config TARGET_P2041RDB
        bool "Support P2041RDB"
        select ARCH_P2041
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select PHYS_64BIT
 
 config TARGET_QEMU_PPCE500
@@ -196,65 +208,76 @@ config TARGET_QEMU_PPCE500
 config TARGET_T1024QDS
        bool "Support T1024QDS"
        select ARCH_T1024
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T1023RDB
        bool "Support T1023RDB"
        select ARCH_T1023
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T1024RDB
        bool "Support T1024RDB"
        select ARCH_T1024
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T1040QDS
        bool "Support T1040QDS"
        select ARCH_T1040
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select PHYS_64BIT
 
 config TARGET_T1040RDB
        bool "Support T1040RDB"
        select ARCH_T1040
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T1040D4RDB
        bool "Support T1040D4RDB"
        select ARCH_T1040
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T1042RDB
        bool "Support T1042RDB"
        select ARCH_T1042
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T1042D4RDB
        bool "Support T1042D4RDB"
        select ARCH_T1042
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T1042RDB_PI
        bool "Support T1042RDB_PI"
        select ARCH_T1042
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T2080QDS
        bool "Support T2080QDS"
        select ARCH_T2080
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T2080RDB
        bool "Support T2080RDB"
        select ARCH_T2080
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
@@ -267,6 +290,7 @@ config TARGET_T2081QDS
 config TARGET_T4160QDS
        bool "Support T4160QDS"
        select ARCH_T4160
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
@@ -279,6 +303,7 @@ config TARGET_T4160RDB
 config TARGET_T4240QDS
        bool "Support T4240QDS"
        select ARCH_T4240
+       select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select SUPPORT_SPL
        select PHYS_64BIT
 
@@ -330,7 +355,9 @@ endchoice
 config ARCH_B4420
        bool
        select E500MC
+       select E6500
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A004477
        select SYS_FSL_ERRATUM_A005871
        select SYS_FSL_ERRATUM_A006379
@@ -343,13 +370,17 @@ config ARCH_B4420
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_B4860
        bool
        select E500MC
+       select E6500
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A004477
        select SYS_FSL_ERRATUM_A005871
        select SYS_FSL_ERRATUM_A006379
@@ -359,15 +390,19 @@ config ARCH_B4860
        select SYS_FSL_ERRATUM_A007075
        select SYS_FSL_ERRATUM_A007186
        select SYS_FSL_ERRATUM_A007212
+       select SYS_FSL_ERRATUM_A007907
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_BSC9131
        bool
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004477
        select SYS_FSL_ERRATUM_A005125
        select SYS_FSL_ERRATUM_ESDHC111
@@ -379,6 +414,7 @@ config ARCH_BSC9131
 config ARCH_BSC9132
        bool
        select FSL_LAW
+       select SYS_FSL_DDR_VER_46
        select SYS_FSL_ERRATUM_A004477
        select SYS_FSL_ERRATUM_A005125
        select SYS_FSL_ERRATUM_A005434
@@ -394,6 +430,7 @@ config ARCH_BSC9132
 config ARCH_C29X
        bool
        select FSL_LAW
+       select SYS_FSL_DDR_VER_46
        select SYS_FSL_ERRATUM_A005125
        select SYS_FSL_ERRATUM_ESDHC111
        select SYS_FSL_HAS_DDR3
@@ -639,6 +676,7 @@ config ARCH_P2041
        select SYS_FSL_ERRATUM_USB14
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
 
@@ -646,6 +684,7 @@ config ARCH_P3041
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004510
        select SYS_FSL_ERRATUM_A004849
        select SYS_FSL_ERRATUM_A005812
@@ -660,6 +699,7 @@ config ARCH_P3041
        select SYS_FSL_ERRATUM_USB14
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
 
@@ -667,6 +707,7 @@ config ARCH_P4080
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004510
        select SYS_FSL_ERRATUM_A004580
        select SYS_FSL_ERRATUM_A004849
@@ -692,6 +733,7 @@ config ARCH_P4080
        select SYS_P4080_ERRATUM_SERDES_A005
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
 
@@ -699,6 +741,7 @@ config ARCH_P5020
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004510
        select SYS_FSL_ERRATUM_A006261
        select SYS_FSL_ERRATUM_DDR_A003
@@ -709,13 +752,16 @@ config ARCH_P5020
        select SYS_FSL_ERRATUM_USB14
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_P5040
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004510
        select SYS_FSL_ERRATUM_A004699
        select SYS_FSL_ERRATUM_A005812
@@ -726,8 +772,10 @@ config ARCH_P5040
        select SYS_FSL_ERRATUM_USB14
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_QEMU_E500
        bool
@@ -736,6 +784,7 @@ config ARCH_T1023
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
@@ -743,6 +792,7 @@ config ARCH_T1023
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5
 
@@ -750,6 +800,7 @@ config ARCH_T1024
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
@@ -757,6 +808,7 @@ config ARCH_T1024
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5
 
@@ -764,6 +816,7 @@ config ARCH_T1040
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008044
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A009663
@@ -772,6 +825,7 @@ config ARCH_T1040
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5
 
@@ -779,6 +833,7 @@ config ARCH_T1042
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008044
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A009663
@@ -787,28 +842,37 @@ config ARCH_T1042
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5
 
 config ARCH_T2080
        bool
        select E500MC
+       select E6500
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A006379
        select SYS_FSL_ERRATUM_A006593
        select SYS_FSL_ERRATUM_A007186
        select SYS_FSL_ERRATUM_A007212
+       select SYS_FSL_ERRATUM_A007815
+       select SYS_FSL_ERRATUM_A007907
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_ESDHC111
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_T2081
        bool
        select E500MC
+       select E6500
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A006379
        select SYS_FSL_ERRATUM_A006593
        select SYS_FSL_ERRATUM_A007186
@@ -817,13 +881,17 @@ config ARCH_T2081
        select SYS_FSL_ERRATUM_ESDHC111
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_T4160
        bool
        select E500MC
+       select E6500
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A004468
        select SYS_FSL_ERRATUM_A005871
        select SYS_FSL_ERRATUM_A006379
@@ -833,13 +901,17 @@ config ARCH_T4160
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config ARCH_T4240
        bool
        select E500MC
+       select E6500
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A004468
        select SYS_FSL_ERRATUM_A005871
        select SYS_FSL_ERRATUM_A006261
@@ -847,11 +919,15 @@ config ARCH_T4240
        select SYS_FSL_ERRATUM_A006593
        select SYS_FSL_ERRATUM_A007186
        select SYS_FSL_ERRATUM_A007798
+       select SYS_FSL_ERRATUM_A007815
+       select SYS_FSL_ERRATUM_A007907
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
+       select SYS_FSL_QORIQ_CHASSIS2
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select SYS_PPC64
 
 config BOOKE
        bool
@@ -868,6 +944,11 @@ config E500MC
        help
                Enble PowerPC E500MC core
 
+config E6500
+       bool
+       help
+               Enable PowerPC E6500 core
+
 config FSL_LAW
        bool
        help
@@ -1027,9 +1108,15 @@ config SYS_FSL_ERRATUM_A007186
 config SYS_FSL_ERRATUM_A007212
        bool
 
+config SYS_FSL_ERRATUM_A007815
+       bool
+
 config SYS_FSL_ERRATUM_A007798
        bool
 
+config SYS_FSL_ERRATUM_A007907
+       bool
+
 config SYS_FSL_ERRATUM_A008044
        bool
 
@@ -1104,6 +1191,12 @@ config SYS_P4080_ERRATUM_SERDES_A001
 config SYS_P4080_ERRATUM_SERDES_A005
        bool
 
+config SYS_FSL_QORIQ_CHASSIS1
+       bool
+
+config SYS_FSL_QORIQ_CHASSIS2
+       bool
+
 config SYS_FSL_NUM_LAWS
        int "Number of local access windows"
        depends on FSL_LAW
@@ -1148,6 +1241,11 @@ config SYS_FSL_NUM_LAWS
                Number of local access windows. This is fixed per SoC.
                If not sure, do not change.
 
+config SYS_FSL_THREADS_PER_CORE
+       int
+       default 2 if E6500
+       default 1
+
 config SYS_NUM_TLBCAMS
        int "Number of TLB CAM entries"
        default 64 if E500MC
@@ -1156,6 +1254,9 @@ config SYS_NUM_TLBCAMS
                Number of TLB CAM entries for Book-E chips. 64 for E500MC,
                16 for other E500 SoCs.
 
+config SYS_PPC64
+       bool
+
 config SYS_PPC_E500_USE_DEBUG_TLB
        bool