#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/u-boot.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING "MPC83XX"
.globl _start
_start: /* time t 0 */
- li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
- nop
- b boot_cold
-
- . = EXC_OFF_SYS_RESET + 0x10
-
- .globl _start_warm
-_start_warm:
- li r21, BOOTFLAG_WARM /* Software reboot */
- b boot_warm
-
-
-boot_cold: /* time t 3 */
lis r4, CONFIG_DEFAULT_IMMR@h
nop
-boot_warm: /* time t 5 */
+
mfmsr r5 /* save msr contents */
/* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
/* run low-level CPU init code (in Flash)*/
bl cpu_init_f
- /* r3: BOOTFLAG */
- mr r3, r21
/* run 1st part of board init code (in Flash)*/
bl board_init_f
+ /* NOTREACHED - board_init_f() does not return */
+
#ifndef CONFIG_NAND_SPL
/*
* Vector Table
lis r3, CONFIG_SYS_IMMR@h
#if defined(CONFIG_WATCHDOG)
- /* Initialise the Wathcdog values and reset it (if req) */
+ /* Initialise the Watchdog values and reset it (if req) */
/*------------------------------------------------------*/
lis r4, CONFIG_SYS_WATCHDOG_VALUE
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
li r4, -0x55C7
sth r4, SWSRR@l(r3)
#else
- /* Disable Wathcdog */
+ /* Disable Watchdog */
/*-------------------*/
lwz r4, SWCRR(r3)
/* Check to see if its enabled for disabling
* Note: requires that all cache bits in
* HID0 are in the low half word.
*/
+#ifndef CONFIG_NAND_SPL
.globl icache_enable
icache_enable:
mfspr r3, HID0
mfspr r3, HID0
rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
blr
+#endif /* !CONFIG_NAND_SPL */
.globl dcache_enable
dcache_enable: