MIPS: Flush huge TLB

[platform/adaptation/renesas_rcar/renesas_kernel.git] / arch / mips / mm / tlb-r4k.c

diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 0d394e0..88dc49c 100644 (file)
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -120,22 +120,30 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 
        if (cpu_context(cpu, mm) != 0) {
                unsigned long size, flags;
+               int huge = is_vm_hugetlb_page(vma);
 
                ENTER_CRITICAL(flags);
-               size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
-               size = (size + 1) >> 1;
+               if (huge) {
+                       start = round_down(start, HPAGE_SIZE);
+                       end = round_up(end, HPAGE_SIZE);
+                       size = (end - start) >> HPAGE_SHIFT;
+               } else {
+                       start = round_down(start, PAGE_SIZE << 1);
+                       end = round_up(end, PAGE_SIZE << 1);
+                       size = (end - start) >> (PAGE_SHIFT + 1);
+               }
                if (size <= current_cpu_data.tlbsize/2) {
                        int oldpid = read_c0_entryhi();
                        int newpid = cpu_asid(cpu, mm);
 
-                       start &= (PAGE_MASK << 1);
-                       end += ((PAGE_SIZE << 1) - 1);
-                       end &= (PAGE_MASK << 1);
                        while (start < end) {
                                int idx;
 
                                write_c0_entryhi(start | newpid);
-                               start += (PAGE_SIZE << 1);
+                               if (huge)
+                                       start += HPAGE_SIZE;
+                               else
+                                       start += (PAGE_SIZE << 1);
                                mtc0_tlbw_hazard();
                                tlb_probe();
                                tlb_probe_hazard();