Merge branch 'mips-next' of http://dev.phrozen.org/githttp/mips-next into mips-for...

[platform/adaptation/renesas_rcar/renesas_kernel.git] / arch / mips / mm / c-r4k.c

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 1d6fee4..0f7d788 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -632,9 +632,6 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
                if (size >= scache_size)
                        r4k_blast_scache();
                else {
-                       unsigned long lsize = cpu_scache_line_size();
-                       unsigned long almask = ~(lsize - 1);
-
                        /*
                         * There is no clearly documented alignment requirement
                         * for the cache instruction on MIPS processors and
@@ -643,9 +640,6 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
                         * hit ops with insufficient alignment.  Solved by
                         * aligning the address to cache line size.
                         */
-                       cache_op(Hit_Writeback_Inv_SD, addr & almask);
-                       cache_op(Hit_Writeback_Inv_SD,
-                                (addr + size - 1) & almask);
                        blast_inv_scache_range(addr, addr + size);
                }
                __sync();
@@ -655,12 +649,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
        if (cpu_has_safe_index_cacheops && size >= dcache_size) {
                r4k_blast_dcache();
        } else {
-               unsigned long lsize = cpu_dcache_line_size();
-               unsigned long almask = ~(lsize - 1);
-
                R4600_HIT_CACHEOP_WAR_IMPL;
-               cache_op(Hit_Writeback_Inv_D, addr & almask);
-               cache_op(Hit_Writeback_Inv_D, (addr + size - 1)  & almask);
                blast_inv_dcache_range(addr, addr + size);
        }
 
@@ -947,7 +936,6 @@ static void __cpuinit probe_pcache(void)
        case CPU_RM7000:
                rm7k_erratum31();
 
-       case CPU_RM9000:
                icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
                c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
                c->icache.ways = 4;
@@ -958,9 +946,7 @@ static void __cpuinit probe_pcache(void)
                c->dcache.ways = 4;
                c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
 
-#if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
                c->options |= MIPS_CPU_CACHE_CDEX_P;
-#endif
                c->options |= MIPS_CPU_PREFETCH;
                break;
 
@@ -1245,7 +1231,6 @@ static void __cpuinit setup_scache(void)
                 return;
 
        case CPU_RM7000:
-       case CPU_RM9000:
 #ifdef CONFIG_RM7000_CPU_SCACHE
                rm7k_sc_init();
 #endif